Contents

 
• General View
• Triple Port Memory
• VME Interface
  • Byte order
  • A32 cycles
  • A24/A16 cycles
  • D32 cycles
  • D16 cycles
  • D8 cycles
  • Read-Modify-Write cycles / Block Transfer
  • Postfetch Mode read cycles
  • Interrupt Acknowledge cycles
• Statusregisters
  • Statusregister 0
  • Statusregister 1
  • Statusregister 2
  • Statusregister 3
• Address Modifier Registers
• Event Handling
• Transputer Analyse/Reset/Error
• References
• Memory Map
• Event Handling Routine
• Data Transfer Rates
• About this document ...