Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:31 2007
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MROD_X_Out
Documentation for entity MROD_X_Out/TTC_Interface
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u1:
Reg1
: a0
Component: u2:
Ser_To_Par
: a0
Component: u8:
Reg1
: a0
Component: u9:
Ser_To_Par
: a0
Component: u3:
TTC_Interrupt
: a0
Component: u17:
Mux2_1
: a0
Component: u13:
EV_BC_ID_Fifo
: a0
Component: u14:
NOrG2
: a0
Component: u15:
Low
: a0
Component: u18:
ShuffleEV_BC_ID_Bits
: a0
Component: u19:
OrG2
: a0
Component: u21:
Extended_EV_ID_Cnt
: a0
Component: u22:
WritePulse
: a0
Component: u16:
EV_BC_ID_Fifo
: a0
Component: u10:
DMA2Sharc
: a0
Component: u11:
InvMultiple
: a0
Component: u12:
Reg
: a0
Component: u0:
AndInv
: a0
Component: u6:
Sync_TTC_Bit
: a0
Component: u4:
TT_Fifo
: a0
Component: u5:
TT_Fifo
: a0