Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:30 2007
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Index
MROD_X_Out
Documentation for entity MROD_X_Out/Ser_To_Par
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u0:
BitCount
: a0
Component: u2:
AndInv
: a0
Component: u4:
AndInv
: a0
Component: u6:
Reg1
: a0
Component: u1:
Reg1Pst
: a0
Component: u3:
Shift_In
: a0
Component: u5:
Inv1
: a0
Component: u7:
Reg1
: a0
Component: u8:
RegEn
: a0