Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:31 2007
Back
Index
MROD_X_Out
Documentation for entity MROD_X_Out/SLINK_Out
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u3:
LinkReset
: a0
Component: u6:
Reg
: a0
Component: u7:
Reg
: a0
Component: u8:
Reg
: a0
Component: u10:
Unequal
: a0
Component: u14:
Cntrl_Status_Reg
: a0
Component: u15:
SLink_FIFO
: a0
Component: u9:
UWEN_Logic
: a0
Component: u2:
Reg1Pst
: a0
Component: u12:
Reg1
: a0
Component: u5:
RegEn
: a0
Component: u17:
OrG2
: a0
Component: u1:
AckGen
: a0
Component: u13:
Tri1
: a0
Component: u16:
DataMux
: a0
Component: u0:
AndG2
: a0
Component: u4:
FlushMode
: a0
Component: u11:
Reg1
: a0
Component: u18:
Reg1
: a0