Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:25 2007
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Index
MROD_X_Out
Documentation for entity MROD_X_Out/Cntrl_Status_Reg
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u10:
WritePulse
: a0
Component: u0:
AndG2
: a0
Component: u1:
HoldFF
: a0
Component: u2:
AndG2
: a0
Component: u3:
RegEn1
: a0
Component: u7:
Inv1
: a0
Component: u8:
Inv1
: a0
Component: u6:
RegEn1
: a0
Component: u11:
Inv1
: a0
Component: u12:
HoldFF
: a0
Component: u14:
AndG2
: a0
Component: u4:
RegEn1
: a0
Component: u5:
Inv1
: a0
Component: u9:
HoldFF
: a0
Component: u17:
AndG2
: a0
Component: u16:
AndG2
: a0
Component: u15:
OrG3
: a0
Component: u19:
Inv1
: a0
Component: u18:
RegEn1
: a0
Component: u20:
Inv1
: a0
Component: u21:
CombReg2d
: a0
Component: u22:
HoldFF
: a0
Component: u23:
AndG2
: a0
Component: u24:
Inv1
: a0
Component: u25:
Inv1
: a0
Component: u26:
Inv1
: a0
Component: u27:
RegEn1
: a0
Component: u13:
AndG2
: a0
Component: u28:
Reg1
: a0
Component: u29:
AndInv
: a0
Component: u30:
Reg1
: a0
Component: u31:
AndInv
: a0