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MROD_X_Out

FPGA

a0

Documentation for process MROD_X_Out/FPGA/a0/VanwegeEaseBug1

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Process 'VanwegeEaseBug1' in architecture 'a0' of entity 'FPGA'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface signals:
    8  -- 
    9  -- WrdL  : in     std_logic_vector(15 downto 0);
   10  -- WrdH  : in     std_logic_vector(15 downto 0);
   11  -- VME_D : out    std_logic_vector(31 downto 0);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  VanwegeEaseBug1: process (WrdL, WrdH) is        -- EASE/HDL sens.list
   16  begin
   17     VME_D(31 Downto 16) <= WrdH;
   18     VME_D(15 Downto 0) <= WrdL;    
   19  end process VanwegeEaseBug1 ;
   20