Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:24 2007
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MGTEVB
Documentation for entity MGTEVB/GenData
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u3:
BufCSM
: a0
Component: u5:
EventHdr
: a0
Component: u1:
RegD
: a0
Component: u4:
RegEV
: a0
Component: u2:
AdrRom
: a0