Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:24 2007
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MGTR
Documentation for entity MGTR/AvDst
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u1:
TLK16
: a0
Component: u2:
RTBuffer
: a0
Component: u3:
LinkCon
: a0