Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:29 2007
Back
Index
MROD_X_Out
Documentation for entity MROD_X_Out/Phase
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u0:
High
: a0
Component: u1:
Reg1
: a0
Component: u2:
AndG2
: a0
Component: u3:
Inv1
: a0
Component: u4:
AndG2
: a0
Component: u5:
Reg1
: a0
Component: u6:
Reg1
: a0