Generated by EASE/HDL for peterj on Mon Jul 02 10:55:27 2007

Documentation for entity MROD_X_Out/IRQ1_Gen

Architectures

Architecture: a0
- Component: u0: WritePulse : a0
- Component: u1: MaskLogic : a0
- Component: u2: RegEn1 : a0
- Component: u3: Inv1 : a0
- Component: u5: HoldFF : a0
- Component: u6: AndG2 : a0
- Component: u7: MaskLogic : a0
- Component: u8: RegEn1 : a0
- Component: u9: Inv1 : a0
- Component: u10: HoldFF : a0
- Component: u11: AndG2 : a0
- Component: u12: MaskLogic : a0
- Component: u13: RegEn1 : a0
- Component: u14: Inv1 : a0
- Component: u15: HoldFF : a0
- Component: u16: AndG2 : a0
- Component: u17: MaskLogic : a0
- Component: u18: RegEn1 : a0
- Component: u19: Inv1 : a0
- Component: u20: HoldFF : a0
- Component: u21: AndG2 : a0
- Component: u22: MaskLogic : a0
- Component: u23: RegEn1 : a0
- Component: u24: Inv1 : a0
- Component: u25: HoldFF : a0
- Component: u26: AndG2 : a0
- Component: u27: MaskLogic : a0
- Component: u28: RegEn1 : a0
- Component: u29: Inv1 : a0
- Component: u30: HoldFF : a0
- Component: u31: AndG2 : a0
- Component: u32: MaskLogic : a0
- Component: u33: RegEn1 : a0
- Component: u34: Inv1 : a0
- Component: u35: HoldFF : a0
- Component: u36: AndG2 : a0
- Component: u37: MaskLogic : a0
- Component: u38: RegEn1 : a0
- Component: u39: Inv1 : a0
- Component: u40: HoldFF : a0
- Component: u41: AndG2 : a0
- Component: u43: Low : a0
- Component: u42: IRQ1 : a0
- Component: u4: InvMultiple : a0
- Component: u44: MaskLogic : a0
- Component: u45: RegEn1 : a0
- Component: u46: Inv1 : a0
- Component: u47: HoldFF : a0
- Component: u48: AndG2 : a0
- Component: u49: MaskLogic : a0
- Component: u50: RegEn1 : a0
- Component: u51: Inv1 : a0
- Component: u52: HoldFF : a0
- Component: u53: AndG2 : a0