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MGTEVB

SLinkPipe

Documentation for architecture MGTEVB/SLinkPipe/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'SLinkPipe'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     LRD    : in     std_logic_vector(31 downto 0);
   11  --     Rst_n  : in     std_logic;
   12  --     SClk   : in     std_logic;
   13  --     SLCtrl : in     std_logic;
   14  --     SLD    : out    std_logic_vector(32 downto 0);
   15  --     SLWE   : out    std_logic;
   16  --     SLWEN  : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of SLinkPipe is
   21  
   22  begin
   23  
   24    -- Create 1 step pipe line (buffer) for data and control signals
   25    -- to decouple all filtering from the next stage (SLink interface).
   26  
   27    prdata:
   28    process (SClk, Rst_n)
   29    begin
   30      if (Rst_n = '0') then
   31        SLD   <= (others => '0');
   32        SLWE  <= '0';
   33      elsif (rising_edge(SClk)) then
   34        SLD   <= SLCtrl & LRD;
   35        SLWE  <= SLWEN;
   36      end if;
   37    end process;
   38  
   39  end architecture a0 ; -- of SLinkPipe
   40  
   41