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MGTEVB

SharcRdFifo

Documentation for architecture MGTEVB/SharcRdFifo/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'SharcRdFifo.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'SharcRdFifo' :
    5  -- 
    6  --   port(
    7  --     Clk     : in     std_logic;
    8  --     Empty   : in     std_logic;
    9  --     RdPulse : out    std_logic;
   10  --     Rd_n    : in     std_logic;
   11  --     Rst_n   : in     std_logic;
   12  --     Sel_n   : in     std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of SharcRdFifo is
   17  
   18    signal QA, QB : std_logic;
   19  
   20  begin
   21  
   22    -- Sel_n and Rd_n must be low to generate a read pulse for the register.
   23    -- In fact this is the request line for the fifo that will be pulsed one cycle.
   24    -- The read pulse (1 clk period) occurs on the leading (falling) edge
   25    -- of the (Sel_N and Rd_n) signal.
   26    -- SHARC Watch out: This only works when Rd_n and/of Sel_n is de-asserted
   27    -- at each new write cycle. This means that the SHARC must add a Hold Cycle
   28    -- to ensure that Rd_n is de-asserted.
   29    -- When a read cycle is started, there is one pulse coming on the rising
   30    -- edge of the clock after the write action (Rd_n adn Sel_n) was initiated.
   31  
   32    RdPulse <= QB and not QA;
   33  
   34    pr1:
   35    process (Clk, Rst_n)
   36    begin
   37      if (Rst_n = '0') then
   38        QA <= '0';
   39        QB <= '0';
   40      elsif (rising_edge(Clk)) then
   41        QA <= Sel_n or Rd_n or Empty;             -- active low and function !
   42        QB <= QA;
   43      end if;
   44    end process;
   45  
   46  end architecture a0 ; -- of SharcRdFifo
   47  
   48