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MGTEVB
MergeSRC| Generated by EASE/HDL for peterj on Mon Jul 02 10:55:24 2007 |
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MGTEVB |
MergeSRC |
| Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'MergeSRC'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- ChanEn : in std_logic_vector(7 downto 0); 11 -- ChanRst : in std_logic_vector(7 downto 0); 12 -- ChanSts : out std_logic_vector(31 downto 0); 13 -- Ena1A : out std_logic; 14 -- Ena1B : out std_logic; 15 -- Ena2A : out std_logic; 16 -- Ena2B : out std_logic; 17 -- Ena3A : out std_logic; 18 -- Ena3B : out std_logic; 19 -- Ena4A : out std_logic; 20 -- Ena4B : out std_logic; 21 -- LDown_n1A : in std_logic; 22 -- LDown_n1B : in std_logic; 23 -- LDown_n2A : in std_logic; 24 -- LDown_n2B : in std_logic; 25 -- LDown_n3A : in std_logic; 26 -- LDown_n3B : in std_logic; 27 -- LDown_n4A : in std_logic; 28 -- LDown_n4B : in std_logic; 29 -- LErr1A : in std_logic; 30 -- LErr1B : in std_logic; 31 -- LErr2A : in std_logic; 32 -- LErr2B : in std_logic; 33 -- LErr3A : in std_logic; 34 -- LErr3B : in std_logic; 35 -- LErr4A : in std_logic; 36 -- LErr4B : in std_logic; 37 -- LRD : out std_logic_v32array(7 downto 0); 38 -- LRD1A : in std_logic_vector(31 downto 0); 39 -- LRD1B : in std_logic_vector(31 downto 0); 40 -- LRD2A : in std_logic_vector(31 downto 0); 41 -- LRD2B : in std_logic_vector(31 downto 0); 42 -- LRD3A : in std_logic_vector(31 downto 0); 43 -- LRD3B : in std_logic_vector(31 downto 0); 44 -- LRD4A : in std_logic_vector(31 downto 0); 45 -- LRD4B : in std_logic_vector(31 downto 0); 46 -- LRX : out std_logic_v32array(7 downto 0); 47 -- LRX1A : in std_logic_vector(31 downto 0); 48 -- LRX1B : in std_logic_vector(31 downto 0); 49 -- LRX2A : in std_logic_vector(31 downto 0); 50 -- LRX2B : in std_logic_vector(31 downto 0); 51 -- LRX3A : in std_logic_vector(31 downto 0); 52 -- LRX3B : in std_logic_vector(31 downto 0); 53 -- LRX4A : in std_logic_vector(31 downto 0); 54 -- LRX4B : in std_logic_vector(31 downto 0); 55 -- RDE : out std_logic_vector(7 downto 0); 56 -- RDE1A : in std_logic; 57 -- RDE1B : in std_logic; 58 -- RDE2A : in std_logic; 59 -- RDE2B : in std_logic; 60 -- RDE3A : in std_logic; 61 -- RDE3B : in std_logic; 62 -- RDE4A : in std_logic; 63 -- RDE4B : in std_logic; 64 -- RDV : out std_logic_vector(7 downto 0); 65 -- RDV1A : in std_logic; 66 -- RDV1B : in std_logic; 67 -- RDV2A : in std_logic; 68 -- RDV2B : in std_logic; 69 -- RDV3A : in std_logic; 70 -- RDV3B : in std_logic; 71 -- RDV4A : in std_logic; 72 -- RDV4B : in std_logic; 73 -- RqRD : in std_logic_vector(7 downto 0); 74 -- RqRD1A : out std_logic; 75 -- RqRD1B : out std_logic; 76 -- RqRD2A : out std_logic; 77 -- RqRD2B : out std_logic; 78 -- RqRD3A : out std_logic; 79 -- RqRD3B : out std_logic; 80 -- RqRD4A : out std_logic; 81 -- RqRD4B : out std_logic; 82 -- RqXD : in std_logic_vector(7 downto 0); 83 -- RxRst1A : out std_logic; 84 -- RxRst1B : out std_logic; 85 -- RxRst2A : out std_logic; 86 -- RxRst2B : out std_logic; 87 -- RxRst3A : out std_logic; 88 -- RxRst3B : out std_logic; 89 -- RxRst4A : out std_logic; 90 -- RxRst4B : out std_logic; 91 -- RxSync1A : in std_logic; 92 -- RxSync1B : in std_logic; 93 -- RxSync2A : in std_logic; 94 -- RxSync2B : in std_logic; 95 -- RxSync3A : in std_logic; 96 -- RxSync3B : in std_logic; 97 -- RxSync4A : in std_logic; 98 -- RxSync4B : in std_logic; 99 -- XDV : out std_logic_vector(7 downto 0); 100 -- XDV1A : in std_logic; 101 -- XDV1B : in std_logic; 102 -- XDV2A : in std_logic; 103 -- XDV2B : in std_logic; 104 -- XDV3A : in std_logic; 105 -- XDV3B : in std_logic; 106 -- XDV4A : in std_logic; 107 -- XDV4B : in std_logic); 108 -- 109 -- EASE/HDL end ---------------------------------------------------------------- 110 111 architecture a0 of MergeSRC is 112 113 begin 114 115 ChanSts <= "00000000" 116 & LErr4B & LErr4A & LErr3B & LErr3A & LErr2B & LErr2A & LErr1B & LErr1A 117 & RxSync4B & RxSync4A & RxSync3B & RxSync3A & RxSync2B & RxSync2A & RxSync1B & RxSync1A 118 & LDown_n4B & LDown_n4A & LDown_n3B & LDown_n3A & LDown_n2B & LDown_n2A & LDown_n1B & LDown_n1A; 119 120 RDE <= RDE4B & RDE4A & RDE3B & RDE3A & RDE2B & RDE2A & RDE1B & RDE1A; 121 RDV <= RDV4B & RDV4A & RDV3B & RDV3A & RDV2B & RDV2A & RDV1B & RDV1A; 122 123 XDV <= XDV4B & XDV4A & XDV3B & XDV3A & XDV2B & XDV2A & XDV1B & XDV1A; 124 125 LRD(7) <= LRD4B; 126 LRD(6) <= LRD4A; 127 LRD(5) <= LRD3B; 128 LRD(4) <= LRD3A; 129 LRD(3) <= LRD2B; 130 LRD(2) <= LRD2A; 131 LRD(1) <= LRD1B; 132 LRD(0) <= LRD1A; 133 134 LRX(7) <= LRX4B; 135 LRX(6) <= LRX4A; 136 LRX(5) <= LRX3B; 137 LRX(4) <= LRX3A; 138 LRX(3) <= LRX2B; 139 LRX(2) <= LRX2A; 140 LRX(1) <= LRX1B; 141 LRX(0) <= LRX1A; 142 143 RxRst4B <= ChanRst(7); 144 RxRst4A <= ChanRst(6); 145 RxRst3B <= ChanRst(5); 146 RxRst3A <= ChanRst(4); 147 RxRst2B <= ChanRst(3); 148 RxRst2A <= ChanRst(2); 149 RxRst1B <= ChanRst(1); 150 RxRst1A <= ChanRst(0); 151 152 -- When a channel is not enabled, set the request bits to always empty the fifos. 153 -- Thus, all data coming from the MGT Fifo will immmediately be flushed. 154 -- The readout controller also checks the enable bits and will ignore 155 -- all data present at the outputs of the fifos. 156 157 RqRD4B <= RqRD(7) when (ChanEn(7) = '1') else '1'; 158 RqRD4A <= RqRD(6) when (ChanEn(6) = '1') else '1'; 159 RqRD3B <= RqRD(5) when (ChanEn(5) = '1') else '1'; 160 RqRD3A <= RqRD(4) when (ChanEn(4) = '1') else '1'; 161 RqRD2B <= RqRD(3) when (ChanEn(3) = '1') else '1'; 162 RqRD2A <= RqRD(2) when (ChanEn(2) = '1') else '1'; 163 RqRD1B <= RqRD(1) when (ChanEn(1) = '1') else '1'; 164 RqRD1A <= RqRD(0) when (ChanEn(0) = '1') else '1'; 165 166 Ena4B <= ChanEn(7); 167 Ena4A <= ChanEn(6); 168 Ena3B <= ChanEn(5); 169 Ena3A <= ChanEn(4); 170 Ena2B <= ChanEn(3); 171 Ena2A <= ChanEn(2); 172 Ena1B <= ChanEn(1); 173 Ena1A <= ChanEn(0); 174 175 end architecture a0 ; -- of MergeSRC 176 177