Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007

Documentation for architecture MROD_X_Out/DecSlowMux/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DecSlowMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr     : in     std_logic_vector(22 downto 0);
   11  --     D_Regs  : out    std_logic_vector(31 downto 0);
   12  --     MS0_n   : in     std_logic;
   13  --     Reg0d   : in     std_logic_vector(10 downto 0);
   14  --     Reg10d  : in     std_logic_vector(31 downto 0);
   15  --     Reg11d  : in     std_logic;
   16  --     Reg12d  : in     std_logic_vector(31 downto 0);
   17  --     Reg13d  : in     std_logic;
   18  --     Reg14d  : in     std_logic_vector(31 downto 0);
   19  --     Reg15d  : in     std_logic;
   20  --     Reg16d  : in     std_logic_vector(31 downto 0);
   21  --     Reg17d  : in     std_logic;
   22  --     Reg18d  : in     std_logic_vector(31 downto 0);
   23  --     Reg19d  : in     std_logic;
   24  --     Reg1Ad  : in     std_logic_vector(31 downto 0);
   25  --     Reg1Bd  : in     std_logic;
   26  --     Reg1Cd  : in     std_logic_vector(31 downto 0);
   27  --     Reg1Dd  : in     std_logic;
   28  --     Reg1Ed  : in     std_logic_vector(31 downto 0);
   29  --     Reg1Fd  : in     std_logic;
   30  --     Reg1d   : in     std_logic_vector(31 downto 0);
   31  --     Reg20d  : in     std_logic_vector(31 downto 0);
   32  --     Reg21d  : in     std_logic;
   33  --     Reg22d  : in     std_logic_vector(31 downto 0);
   34  --     Reg23d  : in     std_logic;
   35  --     Reg24d  : in     std_logic_vector(31 downto 0);
   36  --     Reg25d  : in     std_logic;
   37  --     Reg26d  : in     std_logic_vector(31 downto 0);
   38  --     Reg27d  : in     std_logic;
   39  --     Reg28d  : in     std_logic_vector(31 downto 0);
   40  --     Reg29d  : in     std_logic;
   41  --     Reg2Ad  : in     std_logic_vector(31 downto 0);
   42  --     Reg2Bd  : in     std_logic_vector(31 downto 0);
   43  --     Reg2Cd  : in     std_logic_vector(31 downto 0);
   44  --     Reg2Dd  : in     std_logic_vector(31 downto 0);
   45  --     Reg2Ed  : in     std_logic_vector(31 downto 0);
   46  --     Reg2Fd  : in     std_logic_vector(31 downto 0);
   47  --     Reg2d   : in     std_logic_vector(31 downto 0);
   48  --     Reg30d  : in     std_logic_vector(31 downto 0);
   49  --     Reg3Fd  : in     std_logic_vector(31 downto 0);
   50  --     Reg3d   : in     std_logic_vector(31 downto 0);
   51  --     Reg4d   : in     std_logic_vector(23 downto 0);
   52  --     Reg5d   : in     std_logic_vector(31 downto 0);
   53  --     Reg6d   : in     std_logic_vector(31 downto 0);
   54  --     Reg7d   : in     std_logic_vector(31 downto 0);
   55  --     Reg8d   : in     std_logic_vector(3 downto 0);
   56  --     Reg9d   : in     std_logic_vector(31 downto 0);
   57  --     RegAd   : in     std_logic_vector(31 downto 0);
   58  --     RegBd   : in     std_logic_vector(31 downto 0);
   59  --     RegCd   : in     std_logic_vector(31 downto 0);
   60  --     RegDd   : in     std_logic_vector(31 downto 0);
   61  --     RegEd   : in     std_logic_vector(31 downto 0);
   62  --     RegFd   : in     std_logic;
   63  --     Sel0_n  : out    std_logic;
   64  --     Sel10_n : out    std_logic;
   65  --     Sel11_n : out    std_logic;
   66  --     Sel12_n : out    std_logic;
   67  --     Sel13_n : out    std_logic;
   68  --     Sel14_n : out    std_logic;
   69  --     Sel15_n : out    std_logic;
   70  --     Sel16_n : out    std_logic;
   71  --     Sel17_n : out    std_logic;
   72  --     Sel18_n : out    std_logic;
   73  --     Sel19_n : out    std_logic;
   74  --     Sel1A_n : out    std_logic;
   75  --     Sel1B_n : out    std_logic;
   76  --     Sel1C_n : out    std_logic;
   77  --     Sel1D_n : out    std_logic;
   78  --     Sel1E_n : out    std_logic;
   79  --     Sel1F_n : out    std_logic;
   80  --     Sel1_n  : out    std_logic;
   81  --     Sel20_n : out    std_logic;
   82  --     Sel21_n : out    std_logic;
   83  --     Sel22_n : out    std_logic;
   84  --     Sel23_n : out    std_logic;
   85  --     Sel24_n : out    std_logic;
   86  --     Sel25_n : out    std_logic;
   87  --     Sel26_n : out    std_logic;
   88  --     Sel27_n : out    std_logic;
   89  --     Sel28_n : out    std_logic;
   90  --     Sel29_n : out    std_logic;
   91  --     Sel2A_n : out    std_logic;
   92  --     Sel2B_n : out    std_logic;
   93  --     Sel2C_n : out    std_logic;
   94  --     Sel2D_n : out    std_logic;
   95  --     Sel2E_n : out    std_logic;
   96  --     Sel2F_n : out    std_logic;
   97  --     Sel2_n  : out    std_logic;
   98  --     Sel30_n : out    std_logic;
   99  --     Sel3F_n : out    std_logic;
  100  --     Sel3_n  : out    std_logic;
  101  --     Sel4_n  : out    std_logic;
  102  --     Sel5_n  : out    std_logic;
  103  --     Sel6_n  : out    std_logic;
  104  --     Sel7_n  : out    std_logic;
  105  --     Sel8_n  : out    std_logic;
  106  --     Sel9_n  : out    std_logic;
  107  --     SelA_n  : out    std_logic;
  108  --     SelB_n  : out    std_logic;
  109  --     SelC_n  : out    std_logic;
  110  --     SelD_n  : out    std_logic;
  111  --     SelE_n  : out    std_logic;
  112  --     SelF_n  : out    std_logic);
  113  -- 
  114  -- EASE/HDL end ----------------------------------------------------------------
  115  
  116  architecture a0 of DecSlowMux is
  117  
  118    -- Decode Sharc address lines to write Sharc registers. (maximum 64 regs)
  119    -- Multiplex Sharc registers for read out.
  120  
  121    signal Azero      : std_logic;
  122    signal SelAddress : std_logic_vector(6 downto 0);
  123  
  124  begin
  125  
  126    Azero <= '0' when (MS0_n = '0' and Adr(22 downto 7) = "0000000000000000") else '1';
  127    SelAddress <= Azero & Adr(6 downto 1);
  128  
  129    Sel0_n  <= '0' when (SelAddress = "0000000") else '1';
  130    Sel1_n  <= '0' when (SelAddress = "0000001") else '1';
  131    Sel2_n  <= '0' when (SelAddress = "0000010") else '1';
  132    Sel3_n  <= '0' when (SelAddress = "0000011") else '1';
  133    Sel4_n  <= '0' when (SelAddress = "0000100") else '1';
  134    Sel5_n  <= '0' when (SelAddress = "0000101") else '1';
  135    Sel6_n  <= '0' when (SelAddress = "0000110") else '1';
  136    Sel7_n  <= '0' when (SelAddress = "0000111") else '1';
  137    Sel8_n  <= '0' when (SelAddress = "0001000") else '1';
  138    Sel9_n  <= '0' when (SelAddress = "0001001") else '1';
  139    SelA_n  <= '0' when (SelAddress = "0001010") else '1';
  140    SelB_n  <= '0' when (SelAddress = "0001011") else '1';
  141    SelC_n  <= '0' when (SelAddress = "0001100") else '1';
  142    SelD_n  <= '0' when (SelAddress = "0001101") else '1';
  143    SelE_n  <= '0' when (SelAddress = "0001110") else '1';
  144    SelF_n  <= '0' when (SelAddress = "0001111") else '1';    -- n.u.
  145    Sel10_n <= '0' when (SelAddress = "0010000") else '1';
  146    Sel11_n <= '0' when (SelAddress = "0010001") else '1';    -- n.u.
  147    Sel12_n <= '0' when (SelAddress = "0010010") else '1';
  148    Sel13_n <= '0' when (SelAddress = "0010011") else '1';    -- n.u.
  149    Sel14_n <= '0' when (SelAddress = "0010100") else '1';
  150    Sel15_n <= '0' when (SelAddress = "0010101") else '1';    -- n.u.
  151    Sel16_n <= '0' when (SelAddress = "0010110") else '1';
  152    Sel17_n <= '0' when (SelAddress = "0010111") else '1';    -- n.u.
  153    Sel18_n <= '0' when (SelAddress = "0011000") else '1';
  154    Sel19_n <= '0' when (SelAddress = "0011001") else '1';    -- n.u.
  155    Sel1A_n <= '0' when (SelAddress = "0011010") else '1';
  156    Sel1B_n <= '0' when (SelAddress = "0011011") else '1';    -- n.u.
  157    Sel1C_n <= '0' when (SelAddress = "0011100") else '1';
  158    Sel1D_n <= '0' when (SelAddress = "0011101") else '1';    -- n.u.
  159    Sel1E_n <= '0' when (SelAddress = "0011110") else '1';    -- not used
  160    Sel1F_n <= '0' when (SelAddress = "0011111") else '1';    -- n.u.
  161    Sel20_n <= '0' when (SelAddress = "0100000") else '1';    -- not used
  162    Sel21_n <= '0' when (SelAddress = "0100001") else '1';    -- n.u.
  163    Sel22_n <= '0' when (SelAddress = "0100010") else '1';    -- not used
  164    Sel23_n <= '0' when (SelAddress = "0100011") else '1';    -- n.u.
  165    Sel24_n <= '0' when (SelAddress = "0100100") else '1';    -- not used
  166    Sel25_n <= '0' when (SelAddress = "0100101") else '1';    -- n.u.
  167    Sel26_n <= '0' when (SelAddress = "0100110") else '1';
  168    Sel27_n <= '0' when (SelAddress = "0100111") else '1';    -- n.u.
  169    Sel28_n <= '0' when (SelAddress = "0101000") else '1';
  170    Sel29_n <= '0' when (SelAddress = "0101001") else '1';    -- n.u.
  171    Sel2A_n <= '0' when (SelAddress = "0101010") else '1';
  172    Sel2B_n <= '0' when (SelAddress = "0101011") else '1';
  173    Sel2C_n <= '0' when (SelAddress = "0101100") else '1';
  174    Sel2D_n <= '0' when (SelAddress = "0101101") else '1';
  175    Sel2E_n <= '0' when (SelAddress = "0101110") else '1';    --!
  176    Sel2F_n <= '0' when (SelAddress = "0101111") else '1';    --!
  177    Sel30_n <= '0' when (SelAddress = "0110000") else '1';
  178    Sel3F_n <= '0' when (SelAddress = "0111111") else '1';
  179  
  180    with SelAddress select D_Regs(31 downto 0) <=
  181      x"00000"    & '0'   & Reg0d(10 downto 0)  when "0000000",     -- Sel0_n
  182                            Reg1d(31 downto 0)  when "0000001",     -- Sel1_n
  183                            Reg2d(31 downto 0)  when "0000010",     -- Sel2_n
  184                            Reg3d(31 downto 0)  when "0000011",     -- Sel3_n
  185      x"00"               & Reg4d(23 downto 0)  when "0000100",     -- Sel4_n
  186                            Reg5d(31 downto 0)  when "0000101",     -- Sel5_n
  187                            Reg6d(31 downto 0)  when "0000110",     -- Sel6_n
  188                            Reg7d(31 downto 0)  when "0000111",     -- Sel7_n
  189      x"0000000"          & Reg8d( 3 downto 0)  when "0001000",     -- Sel8_n
  190                            Reg9d(31 downto 0)  when "0001001",     -- Sel9_n
  191                            RegAd(31 downto 0)  when "0001010",     -- SelA_n
  192                            RegBd(31 downto 0)  when "0001011",     -- SelB_n
  193                            RegCd(31 downto 0)  when "0001100",     -- SelC_n
  194                            RegDd(31 downto 0)  when "0001101",     -- SelD_n
  195                            RegEd(31 downto 0)  when "0001110",     -- SelE_n
  196      x"0000000" & "000"  & RegFd               when "0001111",     -- SelF_n 
  197                            Reg10d(31 downto 0) when "0010000",     -- Sel10_n
  198      x"0000000" & "000"  & Reg11d              when "0010001",     -- Sel11_n
  199                            Reg12d(31 downto 0) when "0010010",     -- Sel12_n
  200      x"0000000" &  "000" & Reg13d              when "0010011",     -- Sel13_n
  201                            Reg14d(31 downto 0) when "0010100",     -- Sel14_n
  202      x"0000000" &  "000" & Reg15d              when "0010101",     -- Sel15_n
  203                            Reg16d(31 downto 0) when "0010110",     -- Sel16_n
  204      x"0000000" &  "000" & Reg17d              when "0010111",     -- Sel17_n
  205                            Reg18d(31 downto 0) when "0011000",     -- Sel18_n
  206      x"0000000" &  "000" & Reg19d              when "0011001",     -- Sel19_n
  207                            Reg1Ad(31 downto 0) when "0011010",     -- Sel1A_n
  208      x"0000000" &  "000" & Reg1Bd              when "0011011",     -- Sel1B_n
  209                            Reg1Cd(31 downto 0) when "0011100",     -- Sel1C_n
  210      x"0000000" &  "000" & Reg1Dd              when "0011101",     -- Sel1D_n
  211                            Reg1Ed(31 downto 0) when "0011110",     -- Sel1E_n
  212      x"0000000" &  "000" & Reg1Fd              when "0011111",     -- Sel1F_n
  213                            Reg20d(31 downto 0) when "0100000",     -- Sel20_n
  214      x"0000000" &  "000" & Reg21d              when "0100001",     -- Sel21_n
  215                            Reg22d(31 downto 0) when "0100010",     -- Sel22_n
  216      x"0000000" &  "000" & Reg23d              when "0100011",     -- Sel23_n
  217                            Reg24d(31 downto 0) when "0100100",     -- Sel24_n
  218      x"0000000" &  "000" & Reg25d              when "0100101",     -- Sel25_n
  219                            Reg26d(31 downto 0) when "0100110",     -- Sel26_n
  220      x"0000000" &  "000" & Reg27d              when "0100111",     -- Sel27_n
  221                            Reg28d(31 downto 0) when "0101000",     -- Sel28_n
  222      x"0000000" &  "000" & Reg29d              when "0101001",     -- Sel29_n
  223                            Reg2Ad(31 downto 0) when "0101010",     -- Sel2A_n
  224                            Reg2Bd(31 downto 0) when "0101011",     -- Sel2B_n
  225                            Reg2Cd(31 downto 0) when "0101100",     -- Sel2C_n
  226                            Reg2Dd(31 downto 0) when "0101101",     -- Sel2D_n
  227                            Reg2Ed(31 downto 0) when "0101110",     -- Sel2E_n
  228                            Reg2Fd(31 downto 0) when "0101111",     -- Sel2F_n
  229                            Reg30d(31 downto 0) when "0110000",     -- Sel30_n
  230                            Reg3Fd(31 downto 0) when "0111111",     -- Sel3F_n
  231      --                
  232      x"00000000"                         when others;        -- all others
  233      --
  234  
  235  end architecture a0 ; -- of DecSlowMux
  236  
  237