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MGTEVB

RegSharc

Documentation for architecture MGTEVB/RegSharc/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegSharc'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     initv :  std_logic_vector(31 downto 0) := x"00000000");
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_vector(31 downto 0);
   14  --     Q     : out    std_logic_vector(31 downto 0);
   15  --     Rst_n : in     std_logic;
   16  --     Sel_n : in     std_logic;
   17  --     Wr_n  : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of RegSharc is
   22  
   23  --   generics:
   24  --     initv :  -- initial value of register (on reset)
   25  
   26    signal QA, QB  : std_logic;
   27    signal WrPulse : std_logic;
   28  
   29  begin
   30  
   31    -- Sel_n and Wr_n must be low to generate a write pulse for the register.
   32    -- The write pulse (1 clk period) occurs on the leading (falling) edge
   33    -- of the (Sel_N and Wr_n) signal.
   34    -- SHARC Watch out: This only works when Wr_n and/of Sel_n is de-asserted
   35    -- at each new write cycle. This means that the SHARC must add a Hold Cycle
   36    -- to ensure that Wr_n is de-asserted.
   37    -- When a write cycle is started, there is one pulse coming on the rising
   38    -- edge of the clock after the write action (Wr_n adn Sel_n) was initiated.
   39  
   40    WrPulse <= QB and not QA;
   41  
   42    pr1:
   43    process (Clk, Rst_n)
   44    begin
   45      if (Rst_n = '0') then
   46        QA <= '0';
   47        QB <= '0';
   48      elsif (rising_edge(Clk)) then
   49        QA <= Sel_n or Wr_n;              -- active low and function !
   50        QB <= QA;
   51      end if;
   52    end process;
   53  
   54    pr2:
   55    process (Clk, Rst_n)
   56    begin
   57      if (Rst_n = '0') then
   58        Q <= initv;
   59      elsif (rising_edge(Clk)) then
   60        if (WrPulse = '1') then
   61          Q <= D;
   62        end if;
   63      end if;    
   64    end process;
   65  
   66  end architecture a0 ; -- of RegSharc
   67  
   68