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MGTEVB

Merge4

Documentation for architecture MGTEVB/Merge4/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Merge4'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     HDRdata : out    std_logic_vector(127 downto 0);
   11  --     RegA    : in     std_logic_vector(31 downto 0);
   12  --     RegB    : in     std_logic_vector(31 downto 0);
   13  --     RegC    : in     std_logic_vector(31 downto 0);
   14  --     RegD    : in     std_logic_vector(31 downto 0));
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Merge4 is
   19  
   20  begin
   21  
   22    HDRdata <= RegD & RegC & RegB & RegA;
   23  
   24  end architecture a0 ; -- of Merge4
   25  
   26