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ZBase

RegFV

Documentation for architecture ZBase/RegFV/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RegFV.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RegFV' :
    5  -- 
    6  --   generic(
    7  --     n :  positive := 8 );
    8  --   port(
    9  --     Clk   : in     std_logic;
   10  --     D     : in     std_logic_vector(n-1 downto 0);
   11  --     E_n   : in     std_logic;
   12  --     Q     : out    std_logic_vector(n-1 downto 0);
   13  --     Rst_n : in     std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of RegFV is
   18  
   19  begin
   20  
   21    -- Register with Enable-low.
   22    -- Use as Freeze register (freeze when E_n = '0')
   23  
   24    pr0:
   25    process (Clk, Rst_n)
   26    begin
   27      if (Rst_n = '0') then
   28        Q <= (others => '0');
   29      elsif (rising_edge(Clk)) then
   30        if (E_n = '0') then
   31          Q <= D;
   32        end if;
   33      end if;    
   34    end process;
   35  
   36  end architecture a0 ; -- of RegFV
   37  
   38