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MGTEVB

MGTxRst

Documentation for architecture MGTEVB/MGTxRst/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'MGTxRst'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     TxRst : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of MGTxRst is
   16  
   17    component Wrapped_FDS Is
   18      port(
   19        Q : out std_ulogic;
   20        C : in  std_ulogic;
   21        D : in  std_ulogic;
   22        S : in  std_ulogic
   23        );
   24      end component;
   25  
   26    component Wrapped_FD is
   27      port(
   28        Q : out std_ulogic;
   29        C : in  std_ulogic;
   30        D : in  std_ulogic
   31        );
   32      end component;
   33  
   34    signal out1: std_logic;
   35    signal out2: std_logic;
   36    signal out3: std_logic;
   37    signal out4: std_logic;
   38  
   39     -- Percision Synthesis optimized away the first FF because it has the 'D' input connected to GND.
   40     -- The optimization results in TxRst connected to GlobalGnd.
   41     -- Thus set a NOOPt attribute for the first Flip-Flop
   42     attribute NOOPT: boolean;
   43     attribute NOOPT of Wrapped_FDS: component is TRUE;
   44  
   45  begin
   46  
   47    uc1: Wrapped_FDS port map (D => '0',  C => clk, Q => out1,  S => '0');
   48    uc2: Wrapped_FD  port map (D => out1, C => clk, Q => out2);
   49    uc3: Wrapped_FD  port map (D => out2, C => clk, Q => out3);
   50    uc4: Wrapped_FD  port map (D => out3, C => clk, Q => out4);
   51  
   52    TxRst <= out2 or out3 or out4;
   53  
   54  end architecture a0 ; -- of MGTxRst
   55  
   56