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MGTR

ResetSeq

Documentation for architecture MGTR/ResetSeq/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'ResetSeq.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'ResetSeq' :
    5  -- 
    6  --   port(
    7  --     Clk      : in     std_logic;
    8  --     DRst     : out    std_logic;
    9  --     Lock     : in     std_logic;
   10  --     Reset_n  : in     std_logic;
   11  --     RstSw_n  : in     std_logic;
   12  --     Rst_n    : out    std_logic;
   13  --     RxRst    : out    std_logic;
   14  --     TickUS   : out    std_logic;
   15  --     TxRst    : out    std_logic;
   16  --     XClk     : in     std_logic;
   17  --     doDRst_n : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of ResetSeq is
   22  
   23    signal LTickUs    : std_logic;
   24    signal LockEnd    : std_logic;
   25    signal PwClear_n  : std_logic;
   26    signal RstPhase   : std_logic_vector(3 downto 0);
   27  
   28    constant NTPUS  : unsigned(5 downto 0) := "100000";   --   33 ticks per us.
   29  
   30  begin
   31  
   32    TickUS <= LTickUs;                    -- 1 tick wide pulse every microsecond
   33    DRst   <= not RstPhase(0);            -- inactive at t= 1 us
   34  --TxRst  <= not RstPhase(0);            -- inactive at t= 1 us
   35  --TxRst  <= not RstPhase(1);            -- inactive at t= 2 us
   36    RxRst  <= not RstPhase(2);            -- inactive at t= 3 us
   37    Rst_n  <=     RstPhase(3);            -- inactive at t= 4 us
   38  
   39    ------------------------------------------------------------------------
   40  
   41    pr0:
   42    process (Clk, Reset_n)
   43      variable hold : std_logic_vector (3 downto 0) := "0001";
   44    begin
   45      --if (Reset_n = '0') then     -- only on power-up reset !
   46      --  hold := "0001";           -- set one bit
   47      if (rising_edge(Clk)) then
   48        hold(3 downto 0) := hold(2 downto 0) & '0';
   49      end if;
   50      TxRst <= hold(3) or hold(2) or hold(1);     -- inactive after 4 clockticks
   51    end process;
   52  
   53    pr1:
   54    process (Clk, Reset_n)
   55      variable cntbase : unsigned (5 downto 0);
   56    begin
   57      if (Reset_n = '0') then             -- only on power-up reset !
   58        PwClear_n <= '0';                 -- assert powerclear (low)
   59        LTickUs <= '0';
   60        cntbase := (others => '0');
   61        --cntbase := '0' & NTPUS(5 downto 1);   -- halfway ...
   62      elsif (rising_edge(Clk)) then
   63        if (cntbase = NTPUS) then         -- 33 clockticks per us.
   64          PwClear_n <= '1';               -- deassert powerclear after 1 us.
   65          LTickUs <= '1';                 -- active high pulse (tw=30 ns) every 1 us.
   66          cntbase := (others => '0');
   67        else
   68          LTickUs <= '0';
   69          cntbase := cntbase + 1;
   70        end if;
   71      end if;
   72    end process;
   73  
   74    ---------------------------------------------------------------------------
   75  
   76    -- The following processes work on Power-Up reset and also when
   77    -- the RstSw_n signal is asserted via external pin (switch).
   78  
   79  
   80    pr3:
   81    process (Clk, RstSw_n)
   82    begin
   83      if (RstSw_n = '0') then             -- on power-up reset or switch reset
   84        LockEnd <= '0';
   85      elsif (rising_edge(Clk)) then
   86        if (LTickUs = '1') then
   87          if (Lock = '1') then            -- if (Lock = '1' or CntUs = 200) then
   88            LockEnd <= '1';
   89          end if;
   90        end if;
   91      end if;
   92    end process;
   93  
   94    pr4:
   95    process (Clk, RstSw_n, doDrst_n)
   96    begin
   97      if (RstSw_n = '0') then                     -- on power-up or switch reset
   98        RstPhase <= "000" & doDrst_n;             -- do DCM reset when doDrst_n='0' 
   99      elsif (rising_edge(Clk)) then
  100        if (LTickUs = '1' and PwClear_n = '1') then
  101          RstPhase(0) <= '1';
  102          if (LockEnd = '1') then         --if (LockEnd = '1' or Lock = '1') then
  103            RstPhase(3 downto 1) <= RstPhase(2 downto 0);
  104          end if;
  105        end if;
  106      end if;
  107    end process;
  108  
  109  --  pr5:                                  -- cross the border from SClk to XClk
  110  --  process (XClk, PwClear_n, RstSw_n)
  111  --    variable synca,syncb : std_logic_vector (1 downto 0);
  112  --  begin
  113  --    if (RstSw_n = '0') then              -- on power-up or switch reset
  114  --      synca := "11";
  115  --      syncb := "11";
  116  --    elsif (rising_edge(XClk)) then
  117  --      syncb    := synca;                -- second stage
  118  --      synca(0) := not RstPhase(1);      -- first stage
  119  --      synca(1) := not RstPhase(2);
  120  --    end if;
  121  --    TxRst  <= syncb(0);                 -- inactive at t= 2 us
  122  --    RxRst  <= syncb(1);                 -- inactive at t= 3 us
  123  --  end process;
  124  
  125  end architecture a0 ; -- of ResetSeq
  126  
  127