Back

Index

ZBase

RegDp

Documentation for architecture ZBase/RegDp/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RegDp.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RegDp' :
    5  -- 
    6  --   port(
    7  --     Clk   : in     std_logic;
    8  --     D     : in     std_logic;
    9  --     Pst_n : in     std_logic;
   10  --     Q     : out    std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of RegDp is
   15  
   16  begin
   17  
   18    pr0:
   19    process (Clk, Pst_n)
   20    begin
   21      if (Pst_n = '0') then
   22        Q <= '1';
   23      elsif (rising_edge(Clk)) then
   24        Q <= D;
   25      end if;    
   26    end process;
   27  
   28  end architecture a0 ; -- of RegDp
   29  
   30