Generated by EASE/HDL for peterj on Mon Jul 02 10:55:24 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'RegCntSharc'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- initv : std_logic_vector(31 downto 0) := x"00000000"; 11 -- n : integer := 8); 12 -- port( 13 -- Clk : in std_logic; 14 -- D : in std_logic_vector(n-1 downto 0); 15 -- Inc : in std_logic; 16 -- Q : out std_logic_vector(n-1 downto 0); 17 -- Rst_n : in std_logic; 18 -- Sel_n : in std_logic; 19 -- Wr_n : in std_logic); 20 -- 21 -- EASE/HDL end ---------------------------------------------------------------- 22 23 architecture a0 of RegCntSharc is 24 25 -- generics: 26 -- initv : -- initial value of register (on reset) 27 -- n : -- width of register 28 29 signal QA, QB : std_logic; 30 signal WrPulse : std_logic; 31 32 begin 33 34 -- Sel_n and Wr_n must be low to generate a write pulse for the register. 35 -- The write pulse (1 clk period) occurs on the leading (falling) edge 36 -- of the (Sel_N and Wr_n) signal. 37 -- SHARC Watch out: This only works when Wr_n and/of Sel_n is de-asserted 38 -- at each new write cycle. This means that the SHARC must add a Hold Cycle 39 -- to ensure that Wr_n is de-asserted. 40 -- When a write cycle is started, there is one pulse coming on the rising 41 -- edge of the clock after the write action (Wr_n adn Sel_n) was initiated. 42 43 WrPulse <= QB and not QA; 44 45 pr1: 46 process (Clk, Rst_n) 47 begin 48 if (Rst_n = '0') then 49 QA <= '0'; 50 QB <= '0'; 51 elsif (rising_edge(Clk)) then 52 QA <= Sel_n or Wr_n; -- active low and function ! 53 QB <= QA; 54 end if; 55 end process; 56 57 pr2: 58 process (Clk, Rst_n) 59 variable cnt: unsigned(n-1 downto 0); 60 begin 61 if (Rst_n = '0') then 62 cnt := unsigned(initv(n-1 downto 0)); 63 elsif (rising_edge(Clk)) then 64 if (WrPulse = '1') then 65 cnt(n-1 downto 0) := unsigned(D(n-1 downto 0)); 66 elsif (Inc = '1') then 67 cnt := cnt + 1; 68 end if; 69 end if; 70 Q <= std_logic_vector(cnt); 71 end process; 72 73 end architecture a0 ; -- of RegCntSharc 74 75