Generated by EASE/HDL for peterj on Mon Jul 02 10:55:24 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'ScaleSpy'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Clk : in std_logic; 11 -- Decr : in std_logic; 12 -- EnH : in std_logic; 13 -- EnL : in std_logic; 14 -- LengthFull : in std_logic; 15 -- P : in std_logic_vector(31 downto 0); 16 -- Rst_n : in std_logic; 17 -- SpyActive : out std_logic; 18 -- SpyWEN : out std_logic); 19 -- 20 -- EASE/HDL end ---------------------------------------------------------------- 21 22 architecture a0 of ScaleSpy is 23 24 signal SendSpyEvt : std_logic; 25 26 begin 27 28 -- SpyWEN <= '1' when (SendSpyEvt = '1' and EnH = '1' and EnL = '0') else '0'; 29 30 SpyActive<= SendSpyEvt; 31 32 pr1: 33 process (Clk, Rst_n) 34 variable cnt: unsigned(15 downto 0); 35 begin 36 if (Rst_n = '0') then 37 cnt := (others => '0'); 38 SendSpyEvt <= '0'; 39 SpyWEN <= '0'; 40 elsif (rising_edge(Clk)) then 41 42 -- Pipeline step needed since there is also a pipeline step in the MGTData path 43 if (SendSpyEvt = '1' and EnH = '1' and EnL = '0' and LengthFull = '0') then 44 SpyWEN <= '1'; 45 else 46 SpyWEN <= '0'; 47 end if; 48 49 if (Decr = '1') then 50 if (cnt = 0) then 51 cnt := unsigned(P(15 downto 0)); -- reload counter (only 16 bits) 52 if (P(16) = '1') then 53 SendSpyEvt <= '1'; -- if enabled: send event 54 else 55 SendSpyEvt <= '0'; 56 end if; 57 else 58 cnt := cnt - 1; 59 SendSpyEvt <= '0'; 60 end if; 61 end if; 62 end if; 63 end process; 64 65 end architecture a0 ; -- of ScaleSpy 66 67