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MGTEVB

RegSharcImp

Documentation for architecture MGTEVB/RegSharcImp/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegSharcImp'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     initv :  std_logic_vector(31 downto 0) := x"00000000";
   11  --     imp   :  std_logic_vector(31 downto 0) := x"FFFFFFFF");
   12  --   port(
   13  --     Clk   : in     std_logic;
   14  --     D     : in     std_logic_vector(31 downto 0);
   15  --     Q     : out    std_logic_vector(31 downto 0);
   16  --     Rst_n : in     std_logic;
   17  --     Sel_n : in     std_logic;
   18  --     Wr_n  : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of RegSharcImp is
   23  
   24  --   generics:
   25  --     initv :  -- initial value of register (on reset)
   26  --     imp   :  -- which bits are really implemented
   27  
   28    signal QA, QB  : std_logic;
   29    signal WrPulse : std_logic;
   30  
   31  begin
   32  
   33    -- Sel_n and Wr_n must be low to generate a write pulse for the register.
   34    -- The write pulse (1 clk period) occurs on the leading (falling) edge
   35    -- of the (Sel_N and Wr_n) signal.
   36    -- SHARC Watch out: This only works when Wr_n and/of Sel_n is de-asserted
   37    -- at each new write cycle. This means that the SHARC must add a Hold Cycle
   38    -- to ensure that Wr_n is de-asserted.
   39    -- When a write cycle is started, there is one pulse coming on the rising
   40    -- edge of the clock after the write action (Wr_n adn Sel_n) was initiated.
   41  
   42    WrPulse <= QB and not QA;
   43  
   44    pr1:
   45    process (Clk, Rst_n)
   46    begin
   47      if (Rst_n = '0') then
   48        QA <= '0';
   49        QB <= '0';
   50      elsif (rising_edge(Clk)) then
   51        QA <= Sel_n or Wr_n;              -- active low and function !
   52        QB <= QA;
   53      end if;
   54    end process;
   55  
   56    pr2:
   57    process (Clk, Rst_n)
   58    begin
   59      if (Rst_n = '0') then
   60        Q <= initv;
   61      elsif (rising_edge(Clk)) then
   62        if (WrPulse = '1') then
   63          Q <= D and imp;
   64        end if;
   65      end if;    
   66    end process;
   67  
   68  end architecture a0 ; -- of RegSharcImp
   69  
   70