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MGTEVB

AdrRom

Documentation for architecture MGTEVB/AdrRom/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AdrRom'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     maxv :  positive := 511);
   11  --   port(
   12  --     Addr  : out    std_logic_vector(8 downto 0);
   13  --     Clk   : in     std_logic;
   14  --     EnReg : out    std_logic;
   15  --     Ena   : in     std_logic;
   16  --     FullD : in     std_logic;
   17  --     LWDEN : out    std_logic;
   18  --     Rst_n : in     std_logic;
   19  --     Start : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of AdrRom is
   24  
   25    signal EnAdr    : std_logic;
   26    signal MaxCount : std_logic;
   27    signal Address  : std_logic_vector(8 downto 0);
   28    --constant MaxAdr : std_logic_vector(8 downto 0) := '0' & x"F6";
   29    constant MaxAdr   : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(maxv,9));
   30  
   31  begin
   32  
   33    MaxCount <= '1' when (Address = MaxAdr) else '0';
   34    Addr     <= Address;
   35  
   36    -- note that FullD is actually AlmostFull (one more write allowed).
   37  
   38    -------------------------------------------------------------------------
   39  
   40    pr1:
   41    process (Clk, Rst_n)
   42    begin
   43      if (Rst_n = '0') then
   44        EnAdr <= '0';
   45      elsif (rising_edge(Clk)) then
   46        if (MaxCount = '1') then
   47          EnAdr <= '0';
   48        elsif (Start = '1') then
   49          EnAdr <= '1';
   50        end if;
   51      end if;
   52    end process;
   53  
   54    pr2:
   55    process (Clk, Rst_n)
   56      variable count : unsigned(8 downto 0);
   57      variable phase : std_logic_vector(2 downto 0);
   58    begin
   59      if (Rst_n = '0') then
   60        count := (others => '1');
   61        phase := "000";
   62        EnReg <= '0';
   63        LWDEN <= '0';
   64        --Startup <= '0';
   65      elsif (rising_edge(Clk)) then
   66        if (EnAdr = '0') then
   67          if (phase(2) = '1' or phase(1) = '1' or phase(0) = '1') then
   68            if (FullD = '0' and Ena = '1') then 
   69              if (phase = "110") then
   70                -- on the first tick after EnAdr=0 (end)
   71                EnReg <= '1';
   72              else
   73                EnReg <= '0';
   74              end if;
   75              if (phase = "110" or phase = "100") then
   76                -- on the first or second tick after EnAdr=0 (end)
   77                LWDEN <= '1';
   78              else
   79                LWDEN <= '0';
   80              end if;
   81              phase := phase(1 downto 0) & '0';
   82              -- phase at end: 111, 111, 110, 100, 000.
   83            end if;
   84          else
   85            -- when all words are written after EnAdr=0
   86            count := (others => '1');
   87            EnReg <= '0';
   88            LWDEN <= '0';
   89          end if;
   90          --Startup <= '0';
   91        else
   92          if (MaxCount = '0' and FullD = '0' and Ena = '1') then
   93            count := count + 1;
   94            if (phase(1 downto 0) = "01") then
   95              -- on the first tick after EnAdr=1 (start)
   96              EnReg <= '1';
   97              --Startup <= '1';
   98            end if;
   99            if (phase(1 downto 0) = "11") then
  100              -- on the second tick after EnAdr=1 (start)
  101              EnReg <= '1';
  102              LWDEN <= '1';
  103            end if;
  104            phase := phase(1 downto 0) & EnAdr;
  105            -- phase at start: 000, 001, 011, 111, etc.
  106          else
  107            EnReg <= '0';
  108            LWDEN <= '0';
  109            --Startup <= '0';
  110          end if;
  111        end if;
  112      end if;
  113      Address <= std_logic_vector(count);
  114    end process;
  115  
  116  end architecture a0 ; -- of AdrRom
  117  
  118