Documentation for architecture MGTEVB/MuxControl/a0
VHDL Contents
1 architecture a0 of MuxControl is
52
53 type states_c is (init, nextev, pause0, head1, head2, head3, data, pause1, pause2, trail1, trail2);
54 signal statecon : states_c;
55
56 signal HFullSL : std_logic; signal EventRdy : std_logic; signal ChanActive : std_logic_vector(7 downto 0); signal EvtCur : std_logic_vector(11 downto 0); begin
62
63 ChanActive <= ChanEn and ChanSts(7 downto 0); HFullSL <= '1' when (HFull = '1' or FullD = '1'
70 or (MROD_X_Debug = '1' and (SpyEventFull = '1' or SpyLengthFull = '1' )))
71 else '0';
72 EventRdy <= '1' when
74 ( (EBMGTtest = '0' and EvtAv = '1') or (EBMGTtest = '1' and EvDataRdy = '1') )
75 else '0';
76
77 prConT:
80 process (SClk, Rst_n)
81 variable cntw : unsigned(15 downto 0);
82 variable dats : std_logic_vector(31 downto 0);
83 variable dtav : std_logic;
84 variable chan : unsigned(3 downto 0);
85 variable mask : std_logic_vector(7 downto 0);
86 begin
87 if (Rst_n = '0') then
88 statecon <= init;
89 chan := "0000";
90 mask := x"01";
91 dats := (others => '0');
92 dtav := '0';
93 cntw := x"0002"; ReqD <= '0'; ReqX <= '0'; SxHead <= '0'; SxTrail <= '0'; NextEvt <= '0'; SLCtrl <= '0';
100 EvtCur <= (others => '0'); elsif (rising_edge(SClk)) then
102 case statecon is
103 when init =>
104 chan := "0000";
105 mask := x"01";
106 dats := (others => '0');
107 dtav := '0';
108 cntw := x"0002"; ReqD <= '0'; ReqX <= '0'; SxHead <= '0'; SxTrail <= '0'; if (EBviaMGT = '1' and HFullSL = '0' and EventRdy = '1') then
114 NextEvt <= '1'; statecon <= nextev; else
117 NextEvt <= '0'; statecon <= init;
119 end if;
120 when nextev =>
121 NextEvt <= '0'; SxHead <= '0'; statecon <= pause0;
124 when pause0 =>
125 NextEvt <= '0'; SxHead <= '1'; statecon <= head1;
128 when head1 =>
129 SxHead <= '0'; if (HValid = '1') then dats := HFile; dtav := '1';
133 statecon <= head2;
135 else
136 dtav := '0';
137 statecon <= head1;
138 end if;
139 when head2 =>
140 ReqD <= '0'; if (HValid = '1') then dats := HFile; dtav := '1';
144 ReqX <= '0'; statecon <= head2;
147 elsif (HFullSL = '1') then dtav := '0';
149 ReqX <= '0';
150 statecon <= head2;
151 else
152 dtav := '0';
153 if ((mask and ChanActive) /= x"00") then
154 if (EXempty = '0') then
156 ReqX <= '1'; statecon <= head3;
158 else
159 ReqX <= '0';
160 statecon <= head2;
161 end if;
162 else
163 mask := mask(6 downto 0) & '0';
164 chan := chan + 1;
165 ReqX <= '0'; statecon <= pause1;
167 end if;
168 end if;
169 when head3 =>
170 ReqX <= '0'; if (LastW = '1' or EBempty = '0') then
172 ReqD <= '1'; statecon <= data;
174 else
175 ReqD <= '0';
176 statecon <= head3;
177 end if;
178 when data =>
179 ReqX <= '0'; if (EBvalid = '1' or LastW = '1') then
181 if (MatchLWC = '1') then
182 dats := EBdata(31 downto 24) & x"0" & EXdata(15 downto 12) & x"0" & EXdata(11 downto 0); dtav := '1'; cntw := cntw + 1; elsif (MatchTWC = '1') then
190 dats := EBdata; dtav := '1'; cntw := cntw + 1; elsif (MatchBOEF = '1') then
194 EvtCur <= EBdata(11 downto 0); dtav := '0'; else
197 dats := EBdata; dtav := '1'; cntw := cntw + 1; end if;
201 else
202 dtav := '0'; end if;
204 if (MatchTWC = '1') then
205 ReqD <= '0'; mask := mask(6 downto 0) & '0'; chan := chan + 1;
208 statecon <= pause1;
209 elsif (HFullSL = '1') then ReqD <= '0'; statecon <= pause2; else
213 ReqD <= '1'; statecon <= data; end if;
216 when pause1 =>
217 dtav := '0';
218 ReqD <= '0'; if (HFullSL = '1') then statecon <= pause1; elsif (chan = 8) then SxTrail <= '1'; statecon <= trail1;
224 elsif ((mask and ChanActive) /= x"00") then
225 if (EXempty = '0') then
227 ReqX <= '1'; statecon <= head3;
229 else
230 ReqX <= '0';
231 statecon <= pause1; end if;
233 else
234 mask := mask(6 downto 0) & '0'; chan := chan + 1;
236 statecon <= pause1;
237 end if;
238 when pause2 =>
239 dtav := '0';
240 if (HFullSL = '1') then ReqD <= '0'; statecon <= pause2;
243 else
244 ReqD <= '1'; statecon <= data;
246 end if;
247 when trail1 =>
248 SxTrail <= '0'; ReqD <= '0'; if (HValid = '1') then dats := HFile; dtav := '1';
253 cntw := cntw + 1;
254 statecon <= trail2;
255 else
256 dtav := '0';
257 statecon <= trail1;
258 end if;
259 when trail2 =>
260 if (HValid = '1') then dats := HFile; dtav := '1';
263 cntw := cntw + 1;
264 statecon <= trail2;
265 else
266 dtav := '0';
267 statecon <= init;
268 end if;
269 when others =>
270 dtav := '0';
271 statecon <= init;
272 end case;
273 SLCtrl <= Ctrlbit; end if;
275 Channel <= std_logic_vector(chan(3 downto 0));
276 NDE <= std_logic_vector(cntw); LRD <= dats;
278 SLWEN <= dtav;
279 end process;
280
281 prError:
282 process (SClk, Rst_n)
283 begin
284 if (Rst_n = '0') then
285 EnFilter <= '0';
286 elsif (rising_edge(SClk)) then
287 case statecon is
288 when init =>
289 EnFilter <= '0';
290 when head3 | data =>
291 EnFilter <= '1'; when others =>
294 null;
295 end case;
296 end if;
297 end process;
298
299 end architecture a0 ;