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MROD_X_Out

RdPulseGen

Documentation for architecture MROD_X_Out/RdPulseGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RdPulseGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     MS_Wait :  natural := 0);
   11  --   port(
   12  --     Adr   : in     std_logic;
   13  --     Clk   : in     std_logic;
   14  --     MS_n  : in     std_logic;
   15  --     Rd_n  : in     std_logic;
   16  --     Read  : out    std_logic;
   17  --     Rst_n : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of RdPulseGen is
   22  
   23  BEGIN
   24     Process (Clk, Rst_n, Rd_n, MS_n, Adr)
   25        Variable WaitCnt : Natural Range 0 To 3;
   26     Begin
   27        If Rst_n = '0' Then
   28           Read <= '0';
   29        ElsIf (Rd_n = '0' And MS_n = '0' And Adr = '1') And WaitCnt = MS_Wait Then
   30           Read <= '1';
   31        Else
   32           Read <= '0';
   33        End If;
   34        
   35        If Rst_n = '0' Then
   36           WaitCnt := 0;
   37        ElsIf Rising_Edge(Clk) Then
   38           If NOT (Rd_n = '0' And MS_n = '0' And Adr = '1') Or (WaitCnt = MS_Wait) Then
   39              WaitCnt := 0;
   40           Else
   41              WaitCnt := WaitCnt + 1;
   42           End If;
   43        End If;
   44     End Process;
   45  end architecture a0 ; -- of RdPulseGen
   46