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MakeHeader

Documentation for architecture MGTEVB/MakeHeader/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'MakeHeader'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Ctrlbit   : out    std_logic;
   11  --     EBMGTtest : in     std_logic;
   12  --     ECReset_n : in     std_logic;
   13  --     HDRdata   : in     std_logic_vector(127 downto 0);
   14  --     HFile     : out    std_logic_vector(31 downto 0);
   15  --     HValid    : out    std_logic;
   16  --     Inc_RunN  : out    std_logic;
   17  --     LastEvID  : out    std_logic_vector(31 downto 0);
   18  --     MSE       : in     std_logic_vector(31 downto 0);
   19  --     NDE       : in     std_logic_vector(15 downto 0);
   20  --     Reg2Bd    : in     std_logic_vector(31 downto 0);
   21  --     Rst_n     : in     std_logic;
   22  --     SClk      : in     std_logic;
   23  --     SxHead    : in     std_logic;
   24  --     SxTrail   : in     std_logic;
   25  --     TTCdata   : in     std_logic_vector(63 downto 0);
   26  --     TTCeb     : out    std_logic_vector(23 downto 0));
   27  -- 
   28  -- EASE/HDL end ----------------------------------------------------------------
   29  
   30  architecture a0 of MakeHeader is
   31  
   32    constant CNT_HEAD : integer := 10;    -- 1 (BOF) + 9 (head) + 1 (BOB) {-1}
   33    constant CNT_TRAIL: integer := 5;     -- 1 (EOB) + 4 (status,NSE=1,NDE,SBP) + 1 (EOF) {-1}
   34  
   35    type states is (init, head, pause, trail);
   36    signal state      : states;
   37  
   38    signal HregFile   : std_logic_v32array(10 downto 0);
   39    signal TregFile   : std_logic_v32array(5 downto 0);
   40    signal TrigType   : std_logic_vector(7 downto 0);
   41    signal TestCnt    : std_logic_vector(23 downto 0);
   42    signal EvtNumber  : std_logic_vector(31 downto 0);
   43    signal BcntNumber : std_logic_vector(11 downto 0);
   44    signal TrigTypeNumber : std_logic_vector(7 downto 0);
   45    signal IncDelay   : std_logic_vector(1 downto 0);
   46    signal IncEvtNr   : std_logic;
   47  
   48  begin
   49  
   50    -- Normally extract the EvId/BCId/TrigType from the TTCdata (fifo fed by the TTC system).
   51    -- When in MGTtest mode, use the Extended EvID register (8 bits) and a local counter.
   52    -- MGTtest mode also sets a bit in the MSE trailer word (flagging the testmode-EvID).
   53  
   54    EvtNumber <=
   55      TTCdata(31 downto 0) when (EBMGTtest = '0') else Reg2Bd(31 downto 24) & TestCnt;
   56    BcntNumber <=
   57      TTCdata(43 downto 32) when (EBMGTtest = '0') else (others => '0');
   58    TrigTypeNumber <=
   59      TTCdata(51 downto 44) when (EBMGTtest = '0') else (others => '0');
   60  
   61    prStates:
   62    process (SClk, Rst_n, ECReset_n)
   63      variable cnt : unsigned(3 downto 0);
   64    begin
   65      if (Rst_n = '0' Or ECReset_n = '0') then
   66        cnt := (others => '0');
   67        state <= init;
   68        Inc_RunN <= '0';
   69        IncEvtNr <= '0';
   70      elsif (rising_edge(SClk)) then
   71        case state is
   72        when init =>
   73          cnt := (others => '0');
   74          Inc_RunN <= '0';
   75          IncEvtNr <= '0';
   76          if (SxHead = '1') then
   77            state <= head;
   78          else
   79            state <= init;
   80          end if;
   81        when head =>
   82          if (cnt = 10) then              -- 1 (BOF) + 9 (head) + 1 (BOB)
   83            cnt := (others => '0');
   84            state <= pause;
   85          else
   86            cnt := cnt + 1;
   87            state <= head;
   88          end if;
   89        when pause =>
   90          cnt := (others => '0');
   91          if (SxTrail = '1') then
   92            state <= trail;
   93          else
   94            state <= pause;
   95          end if;
   96        when trail =>
   97          if (cnt = 5) then               -- 1 (EOB) + 4 (sts,NSE,NDE,SBP) + 1 (EOF)
   98            IncEvtNr <= '1';
   99            cnt := (others => '0');
  100            state <= init;
  101          else
  102            cnt := cnt + 1;
  103            state <= trail;
  104          end if;
  105          if (cnt = 4) then
  106            if (Trigtype = x"07") then    -- sweeper event:
  107              Inc_RunN <= '1';            -- incr runnumber after sending all data
  108            end if;
  109          else
  110            Inc_RunN <= '0';
  111          end if;
  112        when others =>
  113          state <= init;
  114        end case;
  115      end if;
  116    end process prStates;
  117  
  118    prFile:
  119    process (SClk, Rst_n, ECReset_n)
  120      variable dat      : std_logic_vector(31 downto 0);
  121      variable ctrlpipe : std_logic_vector(5 downto 0);   -- control bit
  122    begin
  123      if (Rst_n = '0' Or ECReset_n = '0') then
  124        TrigType <= (others => '0');
  125        Ctrlbit <= '0';
  126        HValid <= '0';
  127        HFile  <= (others => '0');
  128        for i in 0 to CNT_HEAD loop
  129           HregFile(i) <= (others => '0');
  130        end loop;
  131        for i in 0 to CNT_TRAIL loop
  132           TregFile(i) <= (others => '0');
  133        end loop;
  134        TTCeb <= (others => '0');
  135        if (Rst_n = '0') then
  136           LastEvID <= (others => '1');           -- Do *not* reset LastEvID on an ECReset_n!
  137      end if;
  138      elsif (rising_edge(SClk)) then
  139        case state is
  140        when init =>
  141          ctrlpipe := "000001";                   -- pipe for control bit (word 1 is BOF)
  142          HValid <= '0';                          -- signal invalid data
  143          HFile <= HregFile(0);                   -- current output frame.
  144          Ctrlbit <= ctrlpipe(0);                 -- send control bit for SLink
  145          --
  146          dat(31 downto  0) := SLINKBOF;          -- Begin Of Frame for SLink
  147          HregFile(0)       <= dat;               --
  148          --
  149          dat(31 downto  0) := HEADMARK;          -- head.mark.
  150          HregFile(1)       <= dat;               -- header frame 1
  151          --
  152          dat(31 downto  0) := HEADSIZE;          -- head.size (fixed 9 words)
  153          HregFile(2)       <= dat;               -- header frame 2
  154          --
  155          dat(31 downto  0) := HDRdata(31 downto 0);    -- format version from VME reg.
  156          HregFile(3)       <= dat;               -- header frame 3
  157          --
  158          dat(31 downto  0) := HDRdata(63 downto 32);   -- module ID from VME reg.
  159          HregFile(4)       <= dat;               -- header frame 4
  160          --
  161          dat(31 downto  0) := HDRdata(95 downto 64);   -- Run number from VME reg.
  162          HregFile(5)       <= dat;               -- header frame 5
  163          --
  164          --dat(31 downto  0) := TTCdata(31 downto 0);    -- full event number from TTC
  165          dat(31 downto  0) := EvtNumber(31 downto 0);  -- full event number from TTC
  166          HregFile(6)       <= dat;               -- header frame 6
  167          --
  168          dat(31 downto 12) := x"00000";          -- zeroes
  169          dat(11 downto  0) := BcntNumber(11 downto 0);  -- bct.num. from TTC
  170          HregFile(7)       <= dat;               -- header frame 7
  171          --
  172          dat(31 downto  8) := x"000000";         -- zeroes
  173          dat( 7 downto  0) := TrigTypeNumber(7 downto 0);   -- trg.typ. from TTC
  174          HregFile(8)       <= dat;               -- header frame 8
  175          TrigType          <= dat(7 downto 0);   -- save for checking later
  176          --
  177          dat(31 downto  0) := HDRdata(127 downto 96);  -- detector type from VME reg.
  178          HregFile(9)       <= dat;               -- header frame 9
  179          --
  180          dat(31 downto 24) := ID_BOB;            -- BOB type identier
  181          --dat(23 downto  0) := TTCdata(23 downto 0);      -- event number from TTC
  182          dat(23 downto  0) := EvtNumber(23 downto 0);    -- event number from TTC
  183          HregFile(10)      <= dat;               -- header BOB frame
  184          TregFile(0)       <= ID_EOB & x"000000";-- EOB with empty wordcount
  185          --
  186          TTCeb(23 downto 12) <= EvtNumber(11 downto  0); -- ECNT
  187          TTCeb(11 downto  0) <= BcntNumber(11 downto 0);   -- BCNT
  188          --
  189        when pause =>
  190          ctrlpipe := "100000";                   -- pipe for control bit (word 6 is EOF)
  191          HValid <= '0';                          -- signal invalid data
  192          HFile <= TregFile(0);                   -- current output frame.
  193          Ctrlbit <= ctrlpipe(0);                 -- send control bit for SLink
  194          --
  195          dat(31 downto 24) := ID_EOB;            -- EOB type identifier
  196          dat(23 downto 16) := x"00";             -- zeroes
  197          dat(15 downto  0) := NDE;               -- NDE (data word count)
  198          TregFile(0)       <= dat;               -- trailer EOB frame
  199          --
  200          dat(31 downto  0) := MSE;               -- status MSE (Mrod Status Element)
  201          TregFile(1)       <= dat;               -- trailer frame 1
  202          --
  203          dat(31 downto  0) := TRAILNSE;          -- NSE number of status elements
  204          TregFile(2)       <= dat;               -- trailer frame 2
  205          --
  206          dat(31 downto 16) := x"0000";           -- zeroes
  207          dat(15 downto  0) := NDE;               -- NDE number of data elements
  208          TregFile(3)       <= dat;               -- trailer frame 3
  209          --
  210          dat(31 downto  0) := TRAILSBP;          -- SBP
  211          TregFile(4)       <= dat;               -- trailer frame 4
  212          --
  213          dat(31 downto  0) := SLINKEOF;          -- End Of Frame for SLink
  214          TregFile(5)       <= dat;               --
  215          --
  216        when head =>
  217          HValid <= '1';                          -- signal valid data
  218          HFile <= HregFile(0);                   -- push last one out
  219          Ctrlbit <= ctrlpipe(0);                 -- send control bit for SLink
  220          for i in 0 to 9 loop
  221            HregFile(i) <= HregFile(i+1);         -- shift registers towards output
  222          end loop;
  223          HregFile(10) <= (others => '1');        -- do not shift in all zeroes
  224          ctrlpipe(5 downto 0) := '0' & ctrlpipe(5 downto 1); -- shift right
  225        LastEvID (31 downto 0) <= EvtNumber(31 downto 0);   -- full event number from TTC
  226          --
  227        when trail =>
  228          HValid <= '1';                          -- signal valid data
  229          HFile <= TregFile(0);                   -- push last one out
  230          Ctrlbit <= ctrlpipe(0);                 -- send control bit for SLink
  231          for i in 0 to 4 loop
  232            TregFile(i) <= TregFile(i+1);         -- shift registers towards output
  233          end loop;
  234          TregFile(5) <= (others => '1');         -- do not shift in all zeroes
  235          ctrlpipe(5 downto 0) := '0' & ctrlpipe(5 downto 1); -- shift right
  236          --
  237        when others =>
  238          HValid <= '0';                          -- signal invalid data
  239          Ctrlbit <= '0';
  240        end case;
  241      end if;
  242    end process;
  243  
  244    prCnt:
  245    process (SClk, Rst_n, ECReset_n)
  246      variable cnt: unsigned(23 downto 0);
  247    begin
  248      if (Rst_n = '0' Or ECReset_n = '0') then
  249        cnt := (others => '0');           -- Run starts with event number 0.
  250        IncDelay <= "00";
  251      elsif (rising_edge(SClk)) then
  252        if (IncDelay(1) = '1') then       -- increment after EOF has been sent
  253          cnt := cnt + 1;
  254        end if;    
  255        IncDelay(1 downto 0) <= IncDelay(0) & IncEvtNr;   -- delay inc signal
  256      end if;    
  257      TestCnt <= std_logic_vector(cnt);
  258    end process;
  259  
  260  end architecture a0 ; -- of MakeHeader
  261  
  262