Generated by EASE/HDL for peterj on Mon Jul 02 10:55:24 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'EventHdr'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Clk : in std_logic; 11 -- FullX : in std_logic; 12 -- LWD : in std_logic_vector(31 downto 0); 13 -- LWDEN : in std_logic; 14 -- LWX : out std_logic_vector(31 downto 0); 15 -- LWXEN : out std_logic; 16 -- Rst_n : in std_logic); 17 -- 18 -- EASE/HDL end ---------------------------------------------------------------- 19 20 architecture a0 of EventHdr is 21 22 constant Wrapcnt : std_logic_vector(11 downto 0) := x"002"; -- number of wrapper words 23 24 begin 25 26 pr1: 27 process (Clk, Rst_n) 28 variable wcnt : std_logic_vector(11 downto 0); 29 begin 30 if (Rst_n = '0') then 31 LWX <= (others => '0'); 32 LWXEN <= '0'; 33 elsif (rising_edge(Clk)) then 34 if (LWDEN = '1') then 35 case LWD(31 downto 24) is 36 when x"8A" => -- look for TWC word 37 wcnt := LWD(11 downto 0) + Wrapcnt; 38 --LWX <= LWD(31 downto 24) & LWD(23 downto 12) & wcnt; -- send trailer 39 LWX <= x"00" & LWD(23 downto 12) & wcnt; -- zeroes & event-id & wcnt 40 LWXEN <= '1'; -- send final wordcount via extended data channel 41 when others => 42 --LWX <= x"00000000"; 43 LWXEN <= '0'; -- nothing to send 44 end case; 45 else 46 LWXEN <= '0'; 47 end if; 48 end if; 49 end process; 50 51 end architecture a0 ; -- of EventHdr 52 53