Documentation for architecture MGTEVB/MakeMSE/a0
VHDL Contents
1 architecture a0 of MakeMSE is
24
25 signal TDCParEr : std_logic;
26 signal GOLParEr : std_logic;
27
28 begin
29
30 TDCParEr <= '1' when (LD(31 downto 28) = Reg2Ad(31 downto 28)) else '0';
31 GOLParEr <= '1' when (LD(31 downto 28) = Reg2Ad(15 downto 12)) else '0';
32
33 prError:
34 process (Clk, Rst_n)
35 variable dats : std_logic_vector(31 downto 0);
36 variable TDCecnt : std_logic_vector(11 downto 0);
37 variable TDCbcnt : std_logic_vector(11 downto 0);
38 begin
39 if (Rst_n = '0') then
40 dats := (others => '0');
41 elsif (rising_edge(Clk)) then
42 if (Valid = '1') then
43 if (MatchBOT = '1') then
44 TDCecnt := LD(23 downto 12); TDCbcnt := LD(11 downto 0); if (TDCecnt /= TTCeb(23 downto 12)) then
47 dats(1) := '1'; end if;
49 if (TDCbcnt /= TTCeb(11 downto 0)) then
50 dats(0) := '1'; end if;
52 elsif (MatchEOT = '1') then
53 TDCecnt := LD(23 downto 12); if (TDCecnt /= TTCeb(23 downto 12)) then
55 dats(1) := '1'; end if;
57 end if;
58 if (TDCParEr = '1') then
59 dats(3) := '1'; dats(16) := '1'; end if;
62 if (GOLParEr = '1') then
63 dats(3) := '1'; dats(17) := '1'; end if;
66 else
67 dats := (others => '0');
68 end if;
69 dats(20) := EBMGTtest; end if;
71 MSE <= dats;
72 end process prError;
73
74 end architecture a0 ;