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MGTEVB
MergeDST| Generated by EASE/HDL for peterj on Mon Jul 02 10:55:24 2007 |
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MGTEVB |
MergeDST |
| Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'MergeDST'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- ChanEn : in std_logic_vector(7 downto 0); 11 -- ChanRst : in std_logic_vector(7 downto 0); 12 -- ChanSts : out std_logic_vector(31 downto 0); 13 -- FullD1A : in std_logic; 14 -- FullD1B : in std_logic; 15 -- FullD2A : in std_logic; 16 -- FullD2B : in std_logic; 17 -- FullD3A : in std_logic; 18 -- FullD3B : in std_logic; 19 -- FullD4A : in std_logic; 20 -- FullD4B : in std_logic; 21 -- LDown_n1A : in std_logic; 22 -- LDown_n1B : in std_logic; 23 -- LDown_n2A : in std_logic; 24 -- LDown_n2B : in std_logic; 25 -- LDown_n3A : in std_logic; 26 -- LDown_n3B : in std_logic; 27 -- LDown_n4A : in std_logic; 28 -- LDown_n4B : in std_logic; 29 -- LErr1A : in std_logic; 30 -- LErr1B : in std_logic; 31 -- LErr2A : in std_logic; 32 -- LErr2B : in std_logic; 33 -- LErr3A : in std_logic; 34 -- LErr3B : in std_logic; 35 -- LErr4A : in std_logic; 36 -- LErr4B : in std_logic; 37 -- LRD : out std_logic_v32array(7 downto 0); 38 -- LRD1A : in std_logic_vector(31 downto 0); 39 -- LRD1B : in std_logic_vector(31 downto 0); 40 -- LRD2A : in std_logic_vector(31 downto 0); 41 -- LRD2B : in std_logic_vector(31 downto 0); 42 -- LRD3A : in std_logic_vector(31 downto 0); 43 -- LRD3B : in std_logic_vector(31 downto 0); 44 -- LRD4A : in std_logic_vector(31 downto 0); 45 -- LRD4B : in std_logic_vector(31 downto 0); 46 -- LRX : out std_logic_v32array(7 downto 0); 47 -- LRX1A : in std_logic_vector(31 downto 0); 48 -- LRX1B : in std_logic_vector(31 downto 0); 49 -- LRX2A : in std_logic_vector(31 downto 0); 50 -- LRX2B : in std_logic_vector(31 downto 0); 51 -- LRX3A : in std_logic_vector(31 downto 0); 52 -- LRX3B : in std_logic_vector(31 downto 0); 53 -- LRX4A : in std_logic_vector(31 downto 0); 54 -- LRX4B : in std_logic_vector(31 downto 0); 55 -- RDE : out std_logic_vector(7 downto 0); 56 -- RDE1A : in std_logic; 57 -- RDE1B : in std_logic; 58 -- RDE2A : in std_logic; 59 -- RDE2B : in std_logic; 60 -- RDE3A : in std_logic; 61 -- RDE3B : in std_logic; 62 -- RDE4A : in std_logic; 63 -- RDE4B : in std_logic; 64 -- RDV : out std_logic_vector(7 downto 0); 65 -- RDV1A : in std_logic; 66 -- RDV1B : in std_logic; 67 -- RDV2A : in std_logic; 68 -- RDV2B : in std_logic; 69 -- RDV3A : in std_logic; 70 -- RDV3B : in std_logic; 71 -- RDV4A : in std_logic; 72 -- RDV4B : in std_logic; 73 -- RqRD : in std_logic_vector(7 downto 0); 74 -- RqRD1A : out std_logic; 75 -- RqRD1B : out std_logic; 76 -- RqRD2A : out std_logic; 77 -- RqRD2B : out std_logic; 78 -- RqRD3A : out std_logic; 79 -- RqRD3B : out std_logic; 80 -- RqRD4A : out std_logic; 81 -- RqRD4B : out std_logic; 82 -- RqXD : in std_logic_vector(7 downto 0); 83 -- RqXD1A : out std_logic; 84 -- RqXD1B : out std_logic; 85 -- RqXD2A : out std_logic; 86 -- RqXD2B : out std_logic; 87 -- RqXD3A : out std_logic; 88 -- RqXD3B : out std_logic; 89 -- RqXD4A : out std_logic; 90 -- RqXD4B : out std_logic; 91 -- RxRst1A : out std_logic; 92 -- RxRst1B : out std_logic; 93 -- RxRst2A : out std_logic; 94 -- RxRst2B : out std_logic; 95 -- RxRst3A : out std_logic; 96 -- RxRst3B : out std_logic; 97 -- RxRst4A : out std_logic; 98 -- RxRst4B : out std_logic; 99 -- RxSync1A : in std_logic; 100 -- RxSync1B : in std_logic; 101 -- RxSync2A : in std_logic; 102 -- RxSync2B : in std_logic; 103 -- RxSync3A : in std_logic; 104 -- RxSync3B : in std_logic; 105 -- RxSync4A : in std_logic; 106 -- RxSync4B : in std_logic; 107 -- XDE : out std_logic_vector(7 downto 0); 108 -- XDE1A : in std_logic; 109 -- XDE1B : in std_logic; 110 -- XDE2A : in std_logic; 111 -- XDE2B : in std_logic; 112 -- XDE3A : in std_logic; 113 -- XDE3B : in std_logic; 114 -- XDE4A : in std_logic; 115 -- XDE4B : in std_logic; 116 -- XDV : out std_logic_vector(7 downto 0); 117 -- XDV1A : in std_logic; 118 -- XDV1B : in std_logic; 119 -- XDV2A : in std_logic; 120 -- XDV2B : in std_logic; 121 -- XDV3A : in std_logic; 122 -- XDV3B : in std_logic; 123 -- XDV4A : in std_logic; 124 -- XDV4B : in std_logic); 125 -- 126 -- EASE/HDL end ---------------------------------------------------------------- 127 128 architecture a0 of MergeDST is 129 130 begin 131 132 ChanSts <= FullD4B & FullD4A & FullD3B & FullD3A & FullD2B & FullD2A & FullD1B & FullD1A 133 & LErr4B & LErr4A & LErr3B & LErr3A & LErr2B & LErr2A & LErr1B & LErr1A 134 & RxSync4B & RxSync4A & RxSync3B & RxSync3A & RxSync2B & RxSync2A & RxSync1B & RxSync1A 135 & LDown_n4B & LDown_n4A & LDown_n3B & LDown_n3A & LDown_n2B & LDown_n2A & LDown_n1B & LDown_n1A; 136 137 RDE <= RDE4B & RDE4A & RDE3B & RDE3A & RDE2B & RDE2A & RDE1B & RDE1A; 138 RDV <= RDV4B & RDV4A & RDV3B & RDV3A & RDV2B & RDV2A & RDV1B & RDV1A; 139 140 XDE <= XDE4B & XDE4A & XDE3B & XDE3A & XDE2B & XDE2A & XDE1B & XDE1A; 141 XDV <= XDV4B & XDV4A & XDV3B & XDV3A & XDV2B & XDV2A & XDV1B & XDV1A; 142 143 LRD(7) <= LRD4B; 144 LRD(6) <= LRD4A; 145 LRD(5) <= LRD3B; 146 LRD(4) <= LRD3A; 147 LRD(3) <= LRD2B; 148 LRD(2) <= LRD2A; 149 LRD(1) <= LRD1B; 150 LRD(0) <= LRD1A; 151 152 LRX(7) <= LRX4B; 153 LRX(6) <= LRX4A; 154 LRX(5) <= LRX3B; 155 LRX(4) <= LRX3A; 156 LRX(3) <= LRX2B; 157 LRX(2) <= LRX2A; 158 LRX(1) <= LRX1B; 159 LRX(0) <= LRX1A; 160 161 RxRst4B <= ChanRst(7); 162 RxRst4A <= ChanRst(6); 163 RxRst3B <= ChanRst(5); 164 RxRst3A <= ChanRst(4); 165 RxRst2B <= ChanRst(3); 166 RxRst2A <= ChanRst(2); 167 RxRst1B <= ChanRst(1); 168 RxRst1A <= ChanRst(0); 169 170 -- When a channel is not enabled, set the request bits to always empty the fifos. 171 -- Thus, all data coming from the MGT Fifo will immmediately be flushed. 172 -- The readout controller also checks the enable bits and will ignore 173 -- all data present at the outputs of the fifos. 174 175 RqRD4B <= RqRD(7) when (ChanEn(7) = '1') else '1'; 176 RqRD4A <= RqRD(6) when (ChanEn(6) = '1') else '1'; 177 RqRD3B <= RqRD(5) when (ChanEn(5) = '1') else '1'; 178 RqRD3A <= RqRD(4) when (ChanEn(4) = '1') else '1'; 179 RqRD2B <= RqRD(3) when (ChanEn(3) = '1') else '1'; 180 RqRD2A <= RqRD(2) when (ChanEn(2) = '1') else '1'; 181 RqRD1B <= RqRD(1) when (ChanEn(1) = '1') else '1'; 182 RqRD1A <= RqRD(0) when (ChanEn(0) = '1') else '1'; 183 184 RqXD4B <= RqXD(7) when (ChanEn(7) = '1') else '1'; 185 RqXD4A <= RqXD(6) when (ChanEn(6) = '1') else '1'; 186 RqXD3B <= RqXD(5) when (ChanEn(5) = '1') else '1'; 187 RqXD3A <= RqXD(4) when (ChanEn(4) = '1') else '1'; 188 RqXD2B <= RqXD(3) when (ChanEn(3) = '1') else '1'; 189 RqXD2A <= RqXD(2) when (ChanEn(2) = '1') else '1'; 190 RqXD1B <= RqXD(1) when (ChanEn(1) = '1') else '1'; 191 RqXD1A <= RqXD(0) when (ChanEn(0) = '1') else '1'; 192 193 end architecture a0 ; -- of MergeDST 194 195