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MGTEVB

EventLen

Documentation for architecture MGTEVB/EventLen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'EventLen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk          : in     std_logic;
   11  --     EnH          : in     std_logic;
   12  --     EnL          : in     std_logic;
   13  --     EvtLen       : out    std_logic_vector(31 downto 0);
   14  --     Full         : in     std_logic;
   15  --     LRD          : in     std_logic_vector(31 downto 0);
   16  --     LengthFull   : out    std_logic;
   17  --     MROD_X_Debug : in     std_logic;
   18  --     Rst_n        : in     std_logic;
   19  --     SpyActive    : in     std_logic;
   20  --     StoreLen     : out    std_logic;
   21  --     TTCeb        : in     std_logic_vector(23 downto 0));
   22  -- 
   23  -- EASE/HDL end ----------------------------------------------------------------
   24  
   25  architecture a0 of EventLen is
   26  
   27    signal SendBOF  : std_logic;
   28    signal SendEOF  : std_logic;
   29    signal SaveFull : std_logic;
   30  
   31  begin
   32  
   33    -- EnH input: enable when High  (= SLink Write Enable)
   34    -- EnL input: enable when Low   (= NOT SLink control bit)
   35    -- Detect begin and end of event ("write" AND "Ctrl bit active" AND "datapattern").
   36  
   37   SendBOF <= '1' when (EnH = '1' and EnL = '1' and LRD = SLINKBOF) else '0';
   38   SendEOF <= '1' when (EnH = '1' and EnL = '1' and LRD = SLINKEOF) else '0';
   39   LengthFull <= SaveFull;
   40  
   41    pr1:
   42    process (Clk, Rst_n)
   43      variable cnt: unsigned(19 downto 0);
   44    begin       
   45      if (Rst_n = '0') then
   46        cnt := (others => '0');
   47        StoreLen <= '0';
   48        SaveFull <= '0';
   49        EvtLen   <= (others => '0');
   50      elsif (rising_edge(Clk)) then
   51        if (SendBOF = '1') then
   52          if (MROD_X_Debug = '0' and Full = '1') then
   53            SaveFull <= '1';      -- check full condition at begin of event.
   54          else
   55            SaveFull <= '0';
   56          end if;
   57          cnt := (others => '0');
   58          StoreLen <= '0';
   59        elsif (SendEOF = '1' and SaveFull = '0') then
   60          EvtLen   <= TTCeb(23 downto 12) & std_logic_vector(cnt);
   61          StoreLen <= SpyActive;
   62        elsif (EnH = '1') then
   63          cnt := cnt + 1;
   64          StoreLen <= '0';
   65        else
   66          StoreLen <= '0';
   67        end if;
   68      end if;
   69    end process;
   70  
   71  end architecture a0 ; -- of EventLen
   72  
   73