Back

Index

MROD_X_Out

SLinkSink

Documentation for architecture MROD_X_Out/SLinkSink/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'SLinkSink'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     FileName :  String := "DataSLink.out");
   11  --   port(
   12  --     Clk    : in     std_logic;
   13  --     UD     : in     std_logic_vector(31 downto 0);
   14  --     UWEN_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of SLinkSink is
   19  
   20  begin
   21  
   22    process (Clk)
   23      file OutpFile: ASCII_Text Open Write_Mode Is FileName;
   24      variable Hex_Str: String(1 To MAX_STRING_LEN);
   25      variable FirstLine: Boolean := True;
   26    begin   
   27      if (FirstLine) then 
   28  --      fprint(OutpFile,"    Time    DataSLink\n");
   29        FirstLine := False;
   30      end if;
   31      if (rising_edge(Clk)) then
   32        if (UWEN_n = '0') then
   33  --        fprint(OutpFile,"%s %s\n",
   34  --          To_String(Now),
   35         fprint(OutpFile,"%s\n",
   36            To_String(To_Bitvector(UD(31 downto 0)), "%x")
   37          );
   38        end if;
   39      end if;
   40    end process;
   41  
   42  end architecture a0 ; -- of SLinkSink
   43  
   44