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MGTEVB

RegSharcCmp

Documentation for architecture MGTEVB/RegSharcCmp/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegSharcCmp'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n     :  positive := 32;
   11  --     initm :  std_logic_vector(31 downto 0) := x"00000000";
   12  --     initp :  std_logic_vector(31 downto 0) := x"00000000";
   13  --     imp   :  std_logic_vector(31 downto 0) := x"FFFFFFFF");
   14  --   port(
   15  --     Clk    : in     std_logic;
   16  --     D      : in     std_logic_vector(31 downto 0);
   17  --     LD     : in     std_logic_vector(31 downto 0);
   18  --     Match  : out    std_logic;
   19  --     QM     : out    std_logic_vector(31 downto 0);
   20  --     QP     : out    std_logic_vector(31 downto 0);
   21  --     Rst_n  : in     std_logic;
   22  --     SelM_n : in     std_logic;
   23  --     SelP_n : in     std_logic;
   24  --     Valid  : in     std_logic;
   25  --     Wr_n   : in     std_logic);
   26  -- 
   27  -- EASE/HDL end ----------------------------------------------------------------
   28  
   29  architecture a0 of RegSharcCmp is
   30  
   31  --   generics:
   32  --     n     :  -- width of register
   33  --     initm :  -- mask    initial value of register (on reset)
   34  --     initp :  -- pattern initial value of register (on reset)
   35  --     imp   :  -- which bits are really implemented
   36  
   37    signal QAM, QBM   : std_logic;
   38    signal WrPulseM   : std_logic;
   39    signal QAP, QBP   : std_logic;
   40    signal WrPulseP   : std_logic;
   41    signal LQP  : std_logic_vector(n-1 downto 0);
   42    signal LQM  : std_logic_vector(n-1 downto 0);
   43    signal QAND : std_logic_vector(n-1 downto 0);
   44    signal QXOR : std_logic_vector(n-1 downto 0);
   45    signal MaskSuccess : std_logic;
   46  
   47  begin
   48  
   49    -- Sel_n and Wr_n must be low to generate a write pulse for the register.
   50    -- The write pulse (1 clk period) occurs on the leading (falling) edge
   51    -- of the (Sel_N and Wr_n) signal.
   52    -- SHARC Watch out: This only works when Wr_n and/of Sel_n is de-asserted
   53    -- at each new write cycle. This means that the SHARC must add a Hold Cycle
   54    -- to ensure that Wr_n is de-asserted.
   55    -- When a write cycle is started, there is one pulse coming on the rising
   56    -- edge of the clock after the write action (Wr_n adn Sel_n) was initiated.
   57  
   58    WrPulseM <= QBM and not QAM;
   59    WrPulseP <= QBP and not QAP;
   60  
   61    QM <= LQM;                            -- register for mask
   62    QP <= LQP;                            -- register for pattern
   63  
   64    QXOR  <= (LD   xor LQP) and imp;      -- compare pattern to data
   65    QAND  <= (QXOR and LQM) and imp;      -- apply mask to cmp-result
   66    Match <= Valid and MaskSuccess;
   67  
   68    --------------------------------------------------------------------------
   69  
   70    pr0:
   71    process (QAND)
   72      variable m : std_logic;
   73    begin
   74      m := '0';
   75      for x in 0 to n-1 loop
   76        if (QAND(x) = '1' and imp(x) = '1') then
   77          m := '1';
   78        end if;
   79      end loop;
   80      MaskSuccess <= not m;        -- if all bits are '0' then MaskSuccess is '1'.
   81    end process;
   82  
   83    pr1a:
   84    process (Clk, Rst_n)
   85    begin
   86      if (Rst_n = '0') then
   87        QAM <= '0';
   88        QBM <= '0';
   89      elsif (rising_edge(Clk)) then
   90        QAM <= (SelM_n or Wr_n);          -- active low and function !
   91        QBM <= QAM;
   92      end if;
   93    end process;
   94  
   95    pr1b:
   96    process (Clk, Rst_n)
   97    begin
   98      if (Rst_n = '0') then
   99        QAP <= '0';
  100        QBP <= '0';
  101      elsif (rising_edge(Clk)) then
  102        QAP <= (SelP_n or Wr_n);          -- active low and function !
  103        QBP <= QAP;
  104      end if;
  105    end process;
  106  
  107    pr2a:
  108    process (Clk, Rst_n)
  109    begin
  110      if (Rst_n = '0') then
  111        LQM <= initm;                     -- local mask register
  112      elsif (rising_edge(Clk)) then
  113        if (WrPulseM = '1') then
  114          LQM <= D and imp;
  115        end if;
  116      end if;    
  117    end process;
  118  
  119    pr2b:
  120    process (Clk, Rst_n)
  121    begin
  122      if (Rst_n = '0') then
  123        LQP <= initp;                     -- local pattern register
  124      elsif (rising_edge(Clk)) then
  125        if (WrPulseP = '1') then
  126          LQP <= D and imp;
  127        end if;
  128      end if;    
  129    end process;
  130  
  131  end architecture a0 ; -- of RegSharcCmp
  132  
  133