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MGTEVB

BufCSM

Documentation for architecture MGTEVB/BufCSM/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'BufCSM'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     AD  : in     std_logic_vector(8 downto 0);
   11  --     Clk : in     std_logic;
   12  --     E   : in     std_logic;
   13  --     Q   : out    std_logic_vector(31 downto 0));
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of BufCSM is
   18  
   19    component rom512w32_01
   20      port (
   21        addr : in std_logic_vector (8 downto 0);
   22        clk  : in std_logic;
   23        dout : out std_logic_vector (31 downto 0);
   24        en   : in std_logic
   25      );
   26    end component;
   27  
   28  begin
   29    
   30    uc1: rom512w32_01
   31    port map (
   32      addr => AD,
   33      clk  => Clk,
   34      dout => Q,
   35      en   => E
   36    );
   37  
   38  end architecture a0 ; -- of BufCSM
   39  
   40