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MGTR

STFlags

Documentation for architecture MGTR/STFlags/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'STFlags'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     EnSD    : out    std_logic;
   11  --     EnSX    : out    std_logic;
   12  --     LRXdata : in     std_logic_vector(31 downto 0);
   13  --     Rst_n   : in     std_logic;
   14  --     XClk    : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of STFlags is
   19  
   20  -- Synchronize the two received bits (flags from destination <receiving> side MGT)
   21  -- to XClk and use them to pause the transfer into the MGT transmitter.
   22    
   23    signal SyncXR1 : std_logic_vector(1 downto 0);
   24  
   25  begin
   26  
   27    pr1:
   28    process (XClk, Rst_n)
   29    begin
   30      if (Rst_n = '0') then
   31        SyncXR1 <= (others => '1');
   32        EnSX <= '1';
   33        EnSD <= '1';
   34      elsif (rising_edge(XClk)) then
   35        SyncXR1 <= not LRXdata(26) & not LRXdata(24);     -- HFull_X & HFull_R;
   36        EnSX    <= SyncXR1(1);
   37        EnSD    <= SyncXR1(0);
   38      end if;
   39    end process;
   40  
   41  end architecture a0 ; -- of STFlags
   42  
   43