Back

Index

ZBase

And23Inv

Documentation for architecture ZBase/And23Inv/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'And23Inv.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'And23Inv' :
    5  -- 
    6  --   port(
    7  --     P1  : in     std_logic;
    8  --     P2n : in     std_logic;
    9  --     P3n : in     std_logic;
   10  --     Q   : out    std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of And23Inv is
   15  
   16  begin
   17  
   18    Q <= P1 and not P2n and not P3n;
   19  
   20  end architecture a0 ; -- of And23Inv
   21  
   22