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ZBase

RegF

Documentation for architecture ZBase/RegF/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RegF.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RegF' :
    5  -- 
    6  --   port(
    7  --     Clk   : in     std_logic;
    8  --     D     : in     std_logic;
    9  --     E_n   : in     std_logic;
   10  --     Q     : out    std_logic;
   11  --     Rst_n : in     std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of RegF is
   16  
   17    -- Register with Enable-low.
   18    -- Use as Freeze register (freeze when E_n = '0')
   19  
   20  begin
   21  
   22    pr0:
   23    process (Clk, Rst_n)
   24    begin
   25      if (Rst_n = '0') then
   26        Q <= '0';
   27      elsif (rising_edge(Clk)) then
   28        if (E_n = '0') then
   29          Q <= D;
   30        end if;
   31      end if;    
   32    end process;
   33  
   34  end architecture a0 ; -- of RegF
   35  
   36