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MGTR

DCM50

Documentation for architecture MGTR/DCM50/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'DCM50.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'DCM50' :
    5  -- 
    6  --   port(
    7  --     DRst : in     std_logic;
    8  --     Lock : out    std_logic;
    9  --     N    : in     std_logic;
   10  --     P    : in     std_logic;
   11  --     XClk : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of DCM50 is
   16  
   17  -- This entity and architecture make a wrapper around the dcm50mhz component.
   18  -- (The component was generated with Xilinx Architecture Wizard.)
   19  -- The locking time (measured on AvNet board) is 4.6 us.
   20  
   21    component dcm50mhz is
   22      port (
   23        RST_IN : in std_logic;
   24        CLKIN_P_IN : in std_logic;
   25        CLKIN_N_IN : in std_logic;
   26        LOCKED_OUT : out std_logic;
   27        CLKDV_OUT : out std_logic;
   28        CLK0_OUT : out std_logic;
   29        CLKIN_IBUFGDS_OUT : out std_logic
   30      );
   31    end component dcm50mhz;
   32  
   33  begin
   34  
   35    uc1: dcm50mhz
   36    port map (
   37      RST_IN      => DRst,
   38      CLKIN_P_IN  => P,
   39      CLKIN_N_IN  => N,
   40      LOCKED_OUT  => Lock,
   41      CLKDV_OUT   => XClk,
   42      CLK0_OUT    => open,
   43      CLKIN_IBUFGDS_OUT => open
   44    );
   45  
   46  end architecture a0 ; -- of DCM50
   47  
   48