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ZBase

RegDV

Documentation for architecture ZBase/RegDV/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegDV'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 32);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_vector(n-1 downto 0);
   14  --     Q     : out    std_logic_vector(n-1 downto 0);
   15  --     Rst_n : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of RegDV is
   20  
   21  begin
   22  
   23    pr0:
   24    process (Clk, Rst_n)
   25    begin
   26      if (Rst_n = '0') then
   27        Q <= (others => '0');
   28      elsif (rising_edge(Clk)) then
   29        Q <= D;
   30      end if;    
   31    end process;
   32  
   33  end architecture a0 ; -- of RegDV
   34  
   35