Generated by EASE/HDL for peterj on Mon Jul 02 10:55:32 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'RegD'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Clk : in std_logic; 11 -- D : in std_logic; 12 -- Q : out std_logic; 13 -- Rst_n : in std_logic); 14 -- 15 -- EASE/HDL end ---------------------------------------------------------------- 16 17 architecture a0 of RegD is 18 19 begin 20 21 pr0: 22 process (Clk, Rst_n) 23 begin 24 if (Rst_n = '0') then 25 Q <= '0'; 26 elsif (rising_edge(Clk)) then 27 Q <= D; 28 end if; 29 end process; 30 31 end architecture a0 ; -- of RegD 32 33