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MGTR

RecWord

Documentation for architecture MGTR/RecWord/a1

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a1' of entity 'RecWord'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Data        : out    std_logic_vector(31 downto 0);
   11  --     IsErrProp   : out    std_logic;
   12  --     RDA         : out    std_logic;
   13  --     RXA         : out    std_logic;
   14  --     Rst_n       : in     std_logic;
   15  --     RxClk       : in     std_logic;
   16  --     RxD         : in     std_logic_vector(15 downto 0);
   17  --     RxIsCarExt  : in     std_logic;
   18  --     RxIsErrProp : in     std_logic;
   19  --     RxIsValid   : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a1 of RecWord is
   24  
   25    signal Toggle     : std_logic;
   26    signal EnMerge    : std_logic;
   27    signal CarExtLSW  : std_logic;
   28    signal CarExtMSW  : std_logic;
   29    signal ErrorLSW   : std_logic;
   30    signal ErrorMSW   : std_logic;
   31    signal IsCarExtd  : std_logic;
   32    signal RcDataMSW  : std_logic_vector(15 downto 0);
   33    signal RcDataLSW  : std_logic_vector(15 downto 0);
   34    signal SaveMSW    : std_logic;
   35    signal ValidData  : std_logic;
   36  
   37  begin
   38  
   39    -- The Xilinx MGT model sends its data in the order
   40    -- din<31:24>, din<23:16>, din<15:8>, din<7:0>.
   41    -- The correct word order is selected in RecWord (no byte remapping).
   42    -- dout0(15 downto  0) <= din(31 downto 16);
   43    -- dout1(15 downto  0) <= din(15 downto 0);
   44    --
   45    --SaveMSW <= '1' when (RxIsValid = '1' and Toggle = '0') else '0';  -- when plain = '1'
   46    --
   47    -- The GOL sends its data in the following order
   48    -- din<7:0>, din<15:8>, din<23:16>, din<31:24>.
   49    -- Thus remap the databus so the byte order is swapped:
   50    -- dout0(15 downto  0) <= din( 7 downto  0),din(15 downto  8);
   51    -- dout1(15 downto  0) <= din(23 downto 16),din(31 downto 24);
   52    --
   53    SaveMSW <= '1' when (RxIsValid = '1' and Toggle = '1') else '0';  -- when plain = '0'
   54  
   55    ValidData <= '1' when (ErrorMSW = '0' and ErrorLSW = '0'
   56                       and CarExtMSW = '0' and CarExtLSW = '0')
   57            else '0';
   58  
   59    ----------------------
   60  
   61    pr0:
   62    process (RxClk, Rst_n)
   63    begin
   64      if (Rst_n = '0') then
   65        Toggle <= '0';
   66      elsif (rising_edge(RxClk)) then
   67        if (RxIsValid = '1' and Toggle = '0') then
   68          Toggle <= '1';
   69        else
   70          Toggle <= '0';
   71        end if;
   72      end if;
   73    end process;
   74  
   75    pr1:
   76    process (RxClk, Rst_n)
   77    begin
   78      if (Rst_n = '0') then
   79        EnMerge   <= '0';
   80        RcDataMSW <= (others => '0');
   81        RcDataLSW <= (others => '0');
   82        CarExtMSW <= '0';
   83        CarExtLSW <= '0';
   84        ErrorMSW  <= '0';
   85        ErrorLSW  <= '0';
   86      elsif (rising_edge(RxClk)) then
   87        if (SaveMSW = '1') then
   88          EnMerge   <= '1';
   89          RcDataMSW <= RxD;
   90          CarExtMSW <= RxIsCarExt;
   91          ErrorMSW  <= RxIsErrProp;
   92        else
   93          EnMerge   <= '0';
   94          RcDataLSW <= RxD;
   95          CarExtLSW <= RxIsCarExt;
   96          ErrorLSW  <= RxIsErrProp;
   97        end if;
   98      end if;
   99    end process;
  100  
  101    pr2:
  102    process (RxClk, Rst_n)
  103    begin
  104      if (Rst_n = '0') then
  105        Data      <= (others => '0');
  106        IsErrProp <= '0';
  107        IsCarExtd <= '0';
  108      elsif (rising_edge(RxClk)) then
  109        if (EnMerge = '1') then
  110          Data      <= RcDataMSW & RcDataLSW;
  111          IsErrProp <= ErrorMSW or ErrorLSW;
  112          IsCarExtd <= CarExtMSW or CarExtLSW;
  113        end if;
  114      end if;
  115    end process;
  116  
  117    pr3:
  118    process (RxClk, Rst_n)
  119    begin
  120      if (Rst_n = '0') then
  121        RDA <= '0';
  122        RXA <= '0';
  123      elsif (rising_edge(RxClk)) then
  124        if (EnMerge = '1') then
  125          RDA <= ValidData and not IsCarExtd;
  126          RXA <= ValidData and IsCarExtd;
  127        else
  128          RDA <= '0';
  129          RXA <= '0';
  130        end if;
  131      end if;
  132    end process;
  133  
  134  end architecture a1 ; -- of RecWord
  135  
  136