Back

Index

ZBase

RegE

Documentation for architecture ZBase/RegE/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RegE.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RegE' :
    5  -- 
    6  --   port(
    7  --     Clk   : in     std_logic;
    8  --     D     : in     std_logic;
    9  --     E     : in     std_logic;
   10  --     Q     : out    std_logic;
   11  --     Rst_n : in     std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of RegE is
   16  
   17  begin
   18  
   19    pr0:
   20    process (Clk, Rst_n)
   21    begin
   22      if (Rst_n = '0') then
   23        Q <= '0';
   24      elsif (rising_edge(Clk)) then
   25        if (E = '1') then
   26          Q <= D;
   27        end if;
   28      end if;    
   29    end process;
   30  
   31  end architecture a0 ; -- of RegE
   32  
   33