Generated by EASE/HDL for peterj on Mon Jul 02 10:55:25 2007

Documentation for architecture MGTR/RxSync/a0

Contents Side Data Generated HDL

Fsm Conditions:

Label Name Usage VHDL
1
Rst_n = '0'
1
RxLossOfSync = SYNC_ACQUIRED
1
Cnt = 20
1
RxLossOfSync /= SYNC_ACQUIRED
1
RxLossOfSync /= SYNC_ACQUIRED

Fsm Actions:

Label Name Usage VHDL
1
RxInSync <= '0';
1
RxInSync <= '0';
1
RxInSync <= '1';
1
RxInSync <= '0';
1
Cnt := 0;
1
Cnt := 0;
1
Cnt := 0;
CntInc1
If (RxLossOfSync = SYNC_ACQUIRED)  and
(RxData = IDLE_Data1 or RxData = IDLE_Data2)  and (RxCharIsK = IDLE_K) Then
   Cnt := Cnt + 1;
End If;