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MGTR

LDownGen

Documentation for architecture MGTR/LDownGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'LDownGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk     : in     std_logic;
   11  --     LDown_n : out    std_logic;
   12  --     Rst_n   : in     std_logic;
   13  --     RxRst   : in     std_logic;
   14  --     RxUp    : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of LDownGen is
   19  
   20  -- State Machine Options:
   21  --  State assignment      : Enumerate.
   22  --  State decoding        : Case construct.
   23  --  Actions on transitions: Clocked.
   24  --  Actions on states     : Clocked.
   25  
   26    type state_type is (Idle, Synced, LinkUp, Hold);
   27    signal state    : state_type;
   28  
   29    signal RxRstDel       : std_logic;
   30    signal RxRstRises     : std_logic;
   31    signal RxUp1, RxUp2   : std_logic;
   32  
   33    signal Cycles     : unsigned (4 downto 0);
   34    signal TimeOut    : std_logic;
   35  
   36  begin
   37  
   38    TimeOut <= '1' when (Cycles = "10100") else '0';  -- 20*25=500ns
   39    RxRstRises <= RxRst and not RxRstDel;     -- active on rising edge of RxRst
   40  
   41    ----------------------------------------------------------------------------
   42  
   43    prSync:
   44    process (Clk, Rst_n)
   45    begin
   46      if (Rst_n = '0') then
   47        RxUp1   <= '0';
   48        RxUp2   <= '0';
   49        RxRstDel <= '0';
   50      elsif (rising_edge(Clk)) then
   51        RxUp1   <= RxUp;
   52        RxUp2   <= RxUp1;         -- synchronize RxUp with this clock
   53        RxRstDel <= RxRst;        -- delay RxRst for edge detection
   54      end if;
   55    end process;
   56  
   57    -- LDown_n (Link Down low active) is to be used for clearing the fifos.
   58  
   59    prStates:
   60    process (Clk, Rst_n)
   61    begin
   62      if (Rst_n = '0') then
   63        state <= Idle;
   64        Cycles <= (others => '0');
   65        LDown_n <= '0';           -- LinkDown (clear fifos)
   66      elsif (rising_edge(Clk)) then
   67        case state is
   68        when Idle =>              -- wait until MGT receiver has synchronized:
   69          Cycles <= (others => '0');
   70          LDown_n <= '0';         -- LinkDown (clear fifos)
   71          if (RxUp2 = '1') then
   72            state <= Synced;      -- MGT_RxInSync turned on
   73          else
   74            state <= Idle;        -- wait ...
   75          end if;
   76        when Synced =>            -- wait until MGT receivers settles:
   77          LDown_n <= '0';         -- LinkDown (clear fifos)
   78          if (Timeout = '1') then
   79            state <= Linkup;      -- when time-out finishes: Link is up.
   80          else
   81            Cycles <= Cycles + 1;
   82            state <= Synced;      -- wait ...
   83          end if;
   84        when LinkUp =>            -- Running ... react on MGT receiver reset:
   85          LDown_n <= '1';         -- LinkDown off (link up)
   86          if (RxRstRises = '1') then
   87            state <= Hold;        -- seeing RxReset ...
   88          elsif (RxUp2 = '0') then
   89            state <= Hold;        -- Link is losing sync ...
   90          else
   91            state <= LinkUp;      -- else Link stays up
   92          end if;
   93        when Hold =>              -- wait until MGT receiver turns off:
   94          LDown_n <= '0';         -- LinkDown (clear fifos)
   95          if (RxUp2 = '0') then
   96            state <= Idle;        -- MGT_RxInSync turns off
   97          else
   98            state <= Hold;        -- wait until Link comes up again 
   99          end if;
  100        when others =>
  101          LDown_n <= '0';         -- LinkDown (clear fifos)
  102          state <= Idle;
  103        end case;
  104      end if;
  105    end process;
  106  
  107  end architecture a0 ; -- of LDownGen
  108  
  109