Generated by EASE/HDL for peterj on Mon Jul 02 10:55:32 2007

Documentation for architecture ZBase/Inv/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'Inv.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'Inv' :
    5  -- 
    6  --   port(
    7  --     I : in     std_logic;
    8  --     Q : out    std_logic);
    9  -- 
   10  -- EASE/HDL end ----------------------------------------------------------------
   11  
   12  architecture a0 of Inv is
   13  
   14  begin
   15  
   16    Q <= not I;
   17  
   18  end architecture a0 ; -- of Inv
   19  
   20