Back

Index

ZBase

And1Inv

Documentation for architecture ZBase/And1Inv/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'And1Inv'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     P1n : in     std_logic;
   11  --     P2  : in     std_logic;
   12  --     Q   : out    std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of And1Inv is
   17  
   18  begin
   19  
   20    Q <= not P1n and P2;
   21  
   22  end architecture a0 ; -- of And1Inv
   23  
   24