Documentation for architecture MGTR/SndWords/a0
VHDL Contents
1 architecture a0 of SndWords is
28
29 type states is (doIdle1, doIdle2, doData, doCarExt, doEData);
30 signal state : states;
31 signal CDS : std_logic_vector(2 downto 0);
32 signal RDX : std_logic_vector(1 downto 0);
33 signal RqData : std_logic;
34 signal RqCExt : std_logic;
35 signal Toggle : std_logic;
36 signal Cycle : unsigned (6 downto 0);
37 signal ForceIdle : std_logic;
38
39 begin
40
41 Data <= LWD when (CDS(0) = '0') else LWX;
42
43 CAV <= CDS(2);
44 DAV <= CDS(1);
45 EAV <= Toggle;
46 RqD <= RDX(1);
47 RqX <= RDX(0);
48
49 RqData <= '1' when (WDE = '0' and EnSD = '1') else '0'; RqCExt <= '1' when (WXE = '0' and EnSX = '1') else '0'; ForceIdle <= '1' when (Cycle(4 downto 0) = 31) else '0';
56 prTrx:
59 process (XClk, Rst_n)
60 begin
61 if (Rst_n = '0') then
62 Toggle <= '0';
63 CDS <= "000"; RDX <= "00"; state <= doIdle1;
66 Cycle <= (others => '0');
67 elsif (rising_edge(XClk)) then
68 if (Toggle = '1') then
69 Toggle <= '0';
70 case state is
71 when doIdle1 =>
72 CDS <= "000"; RDX <= "00"; state <= doIdle2;
75 when doIdle2 =>
76 CDS <= "000"; if (RqData = '1') then
78 RDX <= "10"; state <= doData;
80 elsif (RqCExt = '1') then
81 RDX <= "01"; state <= doCarExt;
83 else
84 RDX <= "00"; state <= doIdle1;
86 end if;
87 when doData =>
88 CDS <= "010"; Cycle <= Cycle + 1;
90 if (ForceIdle = '1') then
91 RDX <= "00"; state <= doIdle1;
93 elsif (RqCExt = '1') then
94 RDX <= "01"; state <= doCarExt;
96 elsif (RqData = '1') then
97 RDX <= "10"; state <= doData;
99 else
100 RDX <= "00"; state <= doIdle1;
102 end if;
103 when doCarExt =>
104 CDS <= "100"; RDX <= "00"; state <= doEData;
107 when doEData =>
108 CDS <= "011"; Cycle <= Cycle + 1;
110 if (RqData = '1') then
111 RDX <= "10"; state <= doData;
113 else
114 RDX <= "00"; state <= doIdle1; end if;
117 when others =>
118 CDS <= "000"; RDX <= "00"; state <= doIdle1;
121 end case;
122 else
123 RDX <= "00"; Toggle <= '1';
125 end if;
126 end if;
127 end process;
128
129 end architecture a0 ;