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MROD_X_Out

IRQ1

Documentation for architecture MROD_X_Out/IRQ1/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'IRQ1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D      : in     std_logic_vector(31 downto 0);
   11  --     IRQ1_n : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of IRQ1 is
   16  begin
   17     Process (D)
   18        Variable m: Std_Logic;
   19     Begin
   20        m := '0';
   21  
   22        -- OR-Gate over bit 0 to 7
   23        For x in 0 to 7 Loop
   24           If D(x) = '1' Then
   25              m := '1';
   26        End If;
   27        End Loop;
   28  
   29        -- OR bit 16, 17
   30        If D(16) = '1' Or D(17) = '1' Then
   31           m := '1';
   32        End If;
   33  
   34        -- Pass the NOR value
   35        IRQ1_n <= NOT m;
   36  
   37     End Process;
   38  end architecture a0 ; -- of IRQ1
   39  
   40