Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'DataMux'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Adr1 : in std_logic; 11 -- D : out std_logic_vector(32 downto 0); 12 -- Data : in std_logic_vector(31 downto 0); 13 -- EBviaMGT : in std_logic; 14 -- MGTData : in std_logic_vector(32 downto 0); 15 -- MGTWr : in std_logic; 16 -- MS3_n : in std_logic; 17 -- SharcWr_n : in std_logic; 18 -- Wr_D : out std_logic); 19 -- 20 -- EASE/HDL end ---------------------------------------------------------------- 21 22 architecture a0 of DataMux is 23 24 signal CTRL_n : std_logic; 25 26 begin 27 28 pr1: 29 process (EBviaMGT, MGTWr, SharcWr_n, MS3_n) 30 begin 31 if (EBviaMGT = '1') then 32 Wr_D <= MGTWr; 33 else 34 Wr_D <= not (SharcWr_n or MS3_n); 35 end if; 36 end process; 37 38 pr2: 39 process (EBviaMGT, MGTData, Data, CTRL_n) 40 begin 41 if (EBviaMGT = '1') then 42 D(31 downto 0) <= MGTData(31 downto 0); 43 D(32) <= not MGTData(32); 44 else 45 D(31 downto 0) <= Data(31 downto 0); 46 D(32) <= CTRL_n; 47 end if; 48 end process; 49 50 -- MS3_n: Sharc addresses S-LINK. 51 -- CTRL_n: is active when write to S-LINK on even address. 52 53 pr3: 54 process (SharcWr_n, MS3_n, Adr1) 55 begin 56 if (SharcWr_n = '0' and MS3_n = '0' and Adr1 = '1') then 57 CTRL_n <= '0'; 58 else 59 CTRL_n <= '1'; 60 end if; 61 end process; 62 63 end architecture a0 ; -- of DataMux 64 65