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MROD_X_Out

DS2401_Shifter

Documentation for architecture MROD_X_Out/DS2401_Shifter/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DS2401_Shifter'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk    : in     std_logic;
   11  --     DS2401 : in     std_logic;
   12  --     Reg6d  : out    std_logic_vector(31 downto 0);
   13  --     Reg7d  : out    std_logic_vector(31 downto 0);
   14  --     Rst_n  : in     std_logic;
   15  --     Sample : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of DS2401_Shifter is
   20  
   21  begin
   22     Process (Clk, Rst_n)
   23        Variable BitString: Std_Logic_Vector(63 downto 0);
   24     Begin       
   25        If Rst_n = '0' Then        
   26           BitString := (Others => '0');      
   27        ElsIf Rising_Edge(Clk) Then
   28           -- LSB is send first (thus shift right)
   29           -- Transmittion order:
   30           -- Family_ID
   31           -- ID
   32           -- CRC
   33           If Sample = '1' Then
   34              BitString(63 downto 0) := TO_X01(DS2401) & BitString(63 downto 1);      -- shift rigth
   35           End If;
   36        End If;
   37        Reg7d(31 downto 24) <= BitString(7 downto 0);     -- Family_ID
   38        Reg7d(23 downto 16) <= BitString(63 downto 56);   -- CRC
   39        Reg7d(15 downto 0) <= BitString(55 downto 40);    -- ID(47 downto 32)
   40        Reg6d <= BitString(39 downto 8);                  -- ID(31 downto 0)
   41     End Process;
   42  end architecture a0 ; -- of DS2401_Shifter
   43  
   44